Mesh Clock Control Logic Cloning for Independent Block Timing
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Solution Overview
Problem
Conventional mesh clock designs are unable to provide independent clock control for each block, partition, or module in a digital circuit design, leading to issues such as on-chip variations and clock skews, which existing synthesis and route flow tools cannot adequately address.
Innovation Solution
The method involves cloning clock control logic (CCL) for each clock tree in a block, allowing each block to have its own CCL, which is achieved by disconnecting the original CCL from sequential gates, generating new clock paths, and connecting multi-source tap cells to ensure independent clock control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional mesh clock design is used, then the clock distribution structure is simple, but independent clock control for each block cannot be achieved
Solution Approach 1:
The patent divides the clock control logic into separate instances for each block. Each block receives a cloned CCL that operates independently, allowing each block to control its own clock signals without interfering with other blocks. This segmentation enables independent clock control while maintaining a structured approach to managing the increased complexity.
Solution Approach 2:
The patent creates cloned instances of the clock control logic for each block. By copying the CCL design and instantiating it multiple times across different blocks, the system achieves independent clock control capability. Each cloned CCL functions as an independent control unit, enabling versatile clock management across the digital circuit design.
2Ease of operation
If each block has its own CCL, then independent operation is enabled, but on-chip variations and clock skews increase
Solution Approach 1:
The patent implements local clock control by providing each block with its own CCL instance that operates independently. This local quality approach allows each block to optimize its clock signals for its specific operational requirements, enabling independent block operation. The local control compensates for on-chip variations by adapting clock signals to local conditions rather than using a single global control mechanism.
3Adaptability or versatility
If CCL is cloned for each clock tree, then independent clock control is achieved, but existing synthesis and route flow tools cannot adequately address the complexity
Solution Approach 1:
The patent designs the cloned CCL instances to maintain compatibility with existing synthesis and route flow tools by adhering to standard design interfaces and conventions. The universal design approach allows the cloned CCLs to be processed by existing EDA tools without requiring complete tool redesign, thereby achieving independent clock control while maintaining a degree of tool compatibility through standardized interfaces.
Data Source
AI summary
A method may include generating a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate. The method may include disconnecting the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate, and generating a second clock path, wherein the mesh is connected to a second CCL. The method may include generating a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree. Finally, the method may include generating a second clock tree in the second clock path between the second CCL and a second sequential gate.