Mesh Gate Electrode for Semiconductor Current Drivability
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Solution Overview
Problem
There is a growing demand for low voltage power devices, such as CMOS devices, where existing semiconductor technologies face challenges in enhancing current drivability and reducing electrical resistance to improve operating speed.
Innovation Solution
The semiconductor device incorporates a silicon substrate with a mesh-type gate electrode and source/drain regions arranged alternately in specific crystal directions, along with embedded regions under the intersections of the gate electrode portions, to enhance current drivability and reduce electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gate electrode structures are used, then manufacturing is simpler, but current drivability and operating speed are insufficient
Solution Approach 1:
The gate electrode is divided into multiple segments arranged in a mesh pattern, with first gate electrodes extending in a first direction and second gate electrodes extending in a second direction orthogonal to the first direction. This segmentation increases the effective gate area and improves current drivability while maintaining manageable structural complexity through systematic arrangement.
Solution Approach 2:
The gate electrode structure transitions from a conventional single-layer planar configuration to a multi-dimensional mesh structure with gate electrodes extending in orthogonal directions. This dimensional expansion increases the effective gate area without proportionally increasing manufacturing complexity, as the mesh pattern follows regular geometric principles.
2Productivity
If source and drain regions are densely arranged to improve current drivability, then parasitic capacitance and contact resistance increase
Solution Approach 1:
Source and drain regions are segmented and alternately arranged in both the first and second directions, creating a periodic pattern that optimizes the balance between current drivability and parasitic effects. This alternating arrangement ensures adequate spacing between adjacent source and drain regions while maximizing the utilization of the active area.
Solution Approach 2:
The source and drain regions are selectively positioned at locations exposed by the mesh openings, with different regions optimized for specific functions. The alternating arrangement in orthogonal directions creates local variations in electrical characteristics that reduce parasitic capacitance while maintaining high current drivability in critical areas.
3Productivity
If mesh-type gate electrode with embedded regions is implemented, then current drivability improves, but manufacturing complexity increases
Solution Approach 1:
The mesh-type gate electrode is constructed by segmenting the gate structure into first and second gate electrodes extending in orthogonal directions, with embedded regions positioned at intersections. This segmentation allows for modular fabrication processes where each component can be formed using standard semiconductor manufacturing techniques.
Solution Approach 2:
Embedded regions are nested within the semiconductor substrate at the intersections of the mesh gate electrodes. This nesting approach integrates additional functional elements into the existing structure without requiring separate fabrication steps, thereby improving operating speed while minimizing increases in manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate of a first conductivity type, a mesh-type gate electrode including first portions extending in a first direction and second portions extending in a second direction crossing the first direction over the substrate. The mesh-type gate structure may have a plurality of openings, and source regions and drain regions of second conductivity type alternately arranged in the first direction and the second direction in the substrate at locations corresponding to the openings.