Mesh Integrated Circuit for Real-Time Sensor Fusion
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Solution Overview
Problem
Current integrated circuit architectures, particularly GPUs, are inadequate for handling the complex machine learning algorithms and real-time processing requirements of autonomous robotics and vehicles, leading to inefficiencies in sensor signal processing and computation tasks such as sensor fusion and path planning.
Innovation Solution
A dense algorithm processing integrated circuit architecture featuring a mesh structure with array cores, border cores, and a hierarchical memory system that enables in-memory computing, direct memory access, and efficient data movement, optimizing the processing of perception data and algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose integrated circuits including CPUs and GPUs are used for sensor processing, then the system has flexibility in handling various computation tasks, but the processing speed and real-time performance are insufficient for complex machine learning algorithms and sensor fusion
Solution Approach 1:
The integrated circuit is divided into multiple array cores, each capable of independent parallel processing. This segmentation allows the system to maintain versatility while achieving high-speed processing through parallel execution of machine learning algorithms and sensor fusion tasks across multiple cores simultaneously.
Solution Approach 2:
The patent introduces a three-dimensional mesh architecture with vertical interconnects between layers, adding a spatial dimension to data flow and processing. This dimensional expansion enables faster access to data and algorithms, significantly improving real-time performance while maintaining the ability to handle diverse computation tasks across the extended architecture.
2Productivity
If traditional GPU architectures are used, then the system can execute large amounts of computations, but the architecture is not optimized for complex machine learning algorithms and sensor fusion tasks
Solution Approach 1:
Each array core in the mesh architecture is equipped with specialized units optimized for specific machine learning operations such as convolution, activation functions, and normalization. This local optimization within each core enables efficient execution of complex algorithms while the overall system maintains high productivity through parallel processing across all cores.
Solution Approach 2:
The mesh architecture provides a universal platform that can execute various machine learning algorithms and sensor fusion tasks through configurable array cores. Each core can be programmed to perform different functions, allowing the system to maintain high productivity across diverse workloads without requiring algorithm-specific hardware designs.
3Adaptability or versatility
If additional and disparate circuitry is assembled to a traditional GPU to handle sensor fusion and path planning, then the processing capabilities are enhanced, but the system complexity increases and inefficiencies in sensor signal processing occur
Solution Approach 1:
The patent merges multiple processing functions including sensor fusion, path planning, and machine learning inference into a single integrated mesh architecture. This consolidation eliminates the need for separate disparate circuitry, reducing system complexity while maintaining enhanced processing capabilities through unified high-speed data flow across the mesh network.
Solution Approach 2:
The mesh architecture acts as an intermediary layer between sensors and output actuators, providing a unified processing platform that efficiently handles sensor fusion and path planning. This intermediate structure simplifies the overall system by replacing multiple specialized circuits with a single versatile mesh network that reduces processing inefficiencies.
Data Source
AI summary
A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.