Mesh Interconnect Interface for Reducing Crosstalk in Chiplets
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Solution Overview
Problem
Current multi-chiplet packaging technologies face challenges with high signal capacitance and crosstalk due to large return currents, leading to increased power consumption and latency, as well as significant silicon die area usage for ground return planes and micro-bumps.
Innovation Solution
The implementation of a mesh interconnect interface with micro-bumps positioned on top of cache arrays and embedded in a multi-layer substrate using through-silicon vias, featuring staggered and interleaved wire connections to reduce cross-capacitance and crosstalk, and eliminating the need for explicit ground or power planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional multi-chiplet packaging with ground return planes is used, then signal transmission is provided, but signal capacitance and power consumption are high
Solution Approach 1:
The patent extracts and eliminates the explicit ground return planes from the interconnect structure. By removing these dedicated ground planes and using the substrate itself as the return path, the design reduces signal capacitance and power consumption while maintaining signal transmission functionality.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support, acts as the return current path for signals, and serves as the embedding medium for through-silicon vias. This multi-functionality eliminates the need for separate ground planes, reducing overall structure complexity and power consumption.
2Area of stationary object
If ground return planes are used for signal transmission, then signal integrity is maintained, but silicon die area is significantly consumed
Solution Approach 1:
The patent removes the dedicated ground return planes that consume significant silicon die area. By extracting this functionality and using the substrate as the return path instead, the design achieves compact area utilization while preserving signal integrity through proper impedance control and crosstalk reduction.
Solution Approach 2:
The patent transitions from a planar ground return structure to a three-dimensional through-silicon via configuration. Signals are routed vertically through the substrate using TSVs, utilizing the vertical dimension to reduce lateral area consumption while maintaining signal integrity through controlled impedance paths.
3Area of stationary object
If densely packed interconnect wires are used, then area is reduced, but cross-capacitance and crosstalk increase
Solution Approach 1:
The patent uses three-dimensional stacking with through-silicon vias to route interconnect wires vertically through the substrate. This dimensional transition allows dense packing while maintaining spatial separation between signal paths, reducing cross-capacitance and crosstalk through increased vertical isolation.
Solution Approach 2:
The substrate acts as an intermediary medium that provides electrical isolation between adjacent interconnect wires. By embedding TSVs in the substrate rather than using planar routing, the substrate material serves as a natural shield that reduces electromagnetic coupling and crosstalk between densely packed signal paths.
Data Source
AI summary
A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.