Configurable Mesh I/O Extension Network Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-core processors, the 'skin effect' and 'affinity restriction' in mesh networks lead to performance issues and design complexity due to uneven traffic distribution and the need for cores to be physically close to input/output devices, causing network congestion and latency variability.
Innovation Solution
The implementation of a mesh I/O extension network, configurable dimension-ordered routing, and stacked dimension-ordered routing mechanisms to reduce the skin effect and affinity restriction by dynamically reconfiguring routing paths and introducing intermediate routing points, thereby distributing traffic more evenly and reducing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dimension-ordered routing is used in mesh networks, then routing simplicity and deadlock-free operation are improved, but network congestion and latency variability worsen due to uneven traffic distribution
Solution Approach 1:
The patent implements dynamic routing policies that adapt the routing dimension order based on current network conditions and traffic patterns. Instead of using a fixed dimension-ordered routing scheme, the system dynamically selects between different routing dimensions and paths, allowing the network to respond to changing traffic demands and avoid congestion hotspots while maintaining routing simplicity.
Solution Approach 2:
The patent changes the routing parameter (dimension order) based on network conditions. By dynamically adjusting which dimension is routed first in the mesh network, the system can optimize traffic distribution and avoid the congestion that occurs with fixed dimension-ordered routing, thereby improving overall network throughput while maintaining the simplicity of deterministic routing.
2Speed
If cores are positioned close to input/output devices, then access speed is improved, but design flexibility and device placement options worsen
Solution Approach 1:
The patent introduces an intermediate extension network layer between the processor cores and the input/output devices. This extension network acts as a mediator that provides fast access paths to I/O devices without requiring cores to be physically adjacent to them. The extension network maintains high-speed connectivity while allowing flexible placement of both cores and I/O devices throughout the chip architecture.
Solution Approach 2:
The patent adds an additional network dimension through the extension network that provides direct access paths to I/O devices. This creates a new routing dimension orthogonal to the standard mesh network, allowing cores to access I/O devices efficiently regardless of their physical distance, thereby decoupling access speed from physical proximity constraints.
3Adaptability or versatility
If extension network is added to connect I/O ports, then I/O access flexibility is improved, but network complexity worsens
Solution Approach 1:
The extension network is designed with multi-functional capabilities that allow it to perform both standard mesh routing and dedicated I/O access functions. By making the extension network universal, the patent avoids adding separate specialized infrastructure, thereby providing flexible I/O mapping capabilities while limiting the increase in overall network complexity.
Solution Approach 2:
The extension network is pre-configured with routing tables and mapping information that enable flexible I/O access without requiring complex runtime decision-making. By performing preliminary configuration of I/O mappings and access paths, the system achieves high flexibility while keeping the operational complexity low, as the extension network follows predetermined routing rules rather than requiring complex dynamic analysis.
Data Source
AI summary
A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.