FPGA DSP Array Overlay Using Mesh PEs for Large Video Streams
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Solution Overview
Problem
Conventional FPGA overlays face inefficiencies in processing large data sets due to limitations in processing and I/O performance, such as the overlap penalty, shift penalty, integer normalization penalty, and I/O inefficiency, which hinder their ability to handle real-time, large-format video processing applications effectively.
Innovation Solution
The proposed solution involves a tile overlay processor (TOP) architecture that arranges processing elements (PEs) in a one-dimensional or bi-dimensional grid, allowing each PE to access neighboring memory elements directly, eliminating redundant data processing and I/O operations through a 'Line-in, Line-out' data flow model, and enabling efficient execution of complex algorithms with reduced hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional vector overlay architectures are used with predefined algorithmic dataflow, then the system can process data with specified priority and individualized instruction sequences, but the array is unable to use a large percentage of FPGA DSP resources and does not exceed a modest number of PEs such as 16
Solution Approach 1:
The system segments the processing architecture into processing elements organized in a mesh topology rather than a linear vector overlay. This segmentation allows each PE to access multiple neighbors independently, enabling scalable expansion beyond 16 PEs while maintaining programmability through the instruction stream interface.
Solution Approach 2:
The patent transitions from a one-dimensional vector overlay architecture to a two-dimensional mesh array architecture. This dimensional change enables significantly more PEs to be accommodated (e.g., 8x8=64 PEs instead of 16) while improving resource utilization of FPGA DSP blocks through the mesh connectivity pattern.
2Ease of operation
If individualized instruction sequences are provided for each PE in conventional architectures, then priority specification is enabled, but connection and data alignment logic requirements become costly and reduce resource utilization
Solution Approach 1:
The mesh array architecture provides a universal interconnection pattern where each PE has standardized connections to its neighbors. This universal topology eliminates the need for individualized connection logic for each PE, reducing overall device complexity while still enabling priority specification through the instruction stream and data flow control.
3Device complexity
If small FPGA arrays are used with conventional vector overlay techniques, then hardware overhead is reduced, but the ability to handle large data sets like 4k or 8k image streams at 60 frames per second is limited
Solution Approach 1:
The mesh array architecture enables each PE to independently access its neighboring PEs' memory elements directly, eliminating the need for centralized data alignment logic. This self-service capability allows small FPGA arrays to efficiently handle large data sets through parallel processing without increasing hardware overhead significantly.
Data Source
AI summary
Techniques and mechanisms described herein include a signal processor implemented as an overlay on a field-programmable gate array (FPGA) device that utilizes special purpose, hardened intellectual property (IP) modules such as memory blocks and digital signal processing (DSP) cores. A Processing Element (PE) is built from one or more DSP cores connected to additional logic. Interconnected as an array, the PEs may operate in a computational model such as Single Instruction-Multiple Thread (SIMT). A software hierarchy is described that transforms the SIMT array into an effective signal processor.