Mesh-Pattern Wiring Resistance Reduction via Localized Enlargement
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Solution Overview
Problem
As microfabrication technology advances, the electrical resistance of power-supply lines in semiconductor devices increases due to reduced wiring width, necessitating a technique to maintain low resistance in mesh-pattern wirings, especially for power-supply and signal lines.
Innovation Solution
The semiconductor device design includes widening power-supply lines at intersection regions to accommodate more conductor plugs, reducing the resistance components by maximizing the area of intersection regions while maintaining minimal interference with adjacent lines, and using a layout method that enlarges specific sides of intersection regions on multiple wiring layers to increase the number of conductor plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the wiring width of power-supply lines is reduced to accommodate more circuits, then the chip area is reduced, but the electrical resistance of the power-supply lines increases
Solution Approach 1:
The patent applies local quality by making the wiring width variable rather than uniform. Specifically, the power-supply lines have a first width in non-intersection regions and a second width (wider than the first) in intersection regions where lines from different wiring layers connect. This local widening at critical intersection points reduces electrical resistance where current density is highest, while maintaining narrower widths in other areas to minimize overall chip area.
2Productivity
If the wiring width is reduced, then more lines can be packed, but the voltage drop increases due to higher resistance
Solution Approach 1:
The patent implements local quality by differentiating wiring width based on functional requirements. Power-supply lines are widened specifically at intersection regions where multiple lines converge, which are the critical points for current flow and voltage stability. This localized widening reduces voltage drop at these critical nodes while allowing the majority of the wiring to maintain narrower dimensions for higher density.
3Reliability
If the wiring width is increased at intersection regions, then the electrical resistance is reduced, but the chip area increases
Solution Approach 1:
The patent applies local quality by restricting width increases to only the necessary intersection regions rather than uniformly widening all power-supply lines. The first wiring layer lines have a first width in non-intersection regions and a second width (wider than the first) only in intersection regions. This selective widening minimizes the total area impact while achieving resistance reduction where it is most needed.
Solution Approach 2:
The patent applies partial action by widening the wiring only partially - specifically at intersection regions - rather than uniformly across the entire length of the power-supply lines. This partial widening is sufficient to reduce the dominant resistance components at connection points without the area penalty of uniform widening throughout the entire wiring structure.
Data Source
AI summary
Disclosed herein is a device that includes: first lines formed on a first wiring layer extending in a first direction; second lines formed on a second wiring layer extending in a second direction; and conductor plugs connecting the first lines to the second lines such that the first and second lines form a mesh-structure wiring. The first lines include first enlarged portions at intersection positions where the first and second lines cross to each other, a width in the second direction of the first enlarged portions is wider than a line width of the first lines at other than the intersection position. The second lines include second enlarged portions at the intersection positions, a width in the first direction of the second enlarged portions is wider than a line width of the second lines at other than the intersection position.