Meshed Common Line Reduces Parasitic Capacitance in TFT-LCD
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Solution Overview
Problem
The conventional half source driver architecture in TFT-LCD panels results in significant capacitance coupling between common lines and data lines, leading to bright-dark lines and poor display quality due to the H-shaped common line design.
Innovation Solution
An active device array substrate with a meshed common line design featuring ring-shaped patterns under the display units, where each ring-shaped pattern consists of semi-ring-shaped patterns on either side of a data line, reducing the overlaying area and thus minimizing parasitic capacitance between data lines and the common line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an H-shaped common line design is used in a TFT-LCD panel with half source driver architecture, then the layout is simplified and manufacturing is easier, but significant capacitance coupling occurs between the common line and data lines, leading to voltage drift and display quality degradation
Solution Approach 1:
The common line is divided into multiple segments (first common line segments and second common line segments) that are arranged in an interlaced pattern with data lines, rather than using a continuous H-shaped design. This segmentation reduces the overlapping area between common lines and data lines, thereby reducing parasitic capacitance coupling while maintaining manufacturing feasibility.
Solution Approach 2:
The common line structure transitions from a planar H-shaped design to a three-dimensional meshed structure with multiple layers. The first and second common line segments are arranged in different spatial dimensions and interconnected, creating a meshed configuration that reduces coupling with data lines while maintaining electrical connectivity.
2Area of stationary object
If the common line is positioned close to data lines for compact layout, then space utilization is improved, but the coupling effect between common line and data lines increases, causing voltage instability
Solution Approach 1:
The common line is segmented into multiple sections that can be independently routed through the pixel array. These segments are distributed throughout the array in a meshed pattern, allowing the common line to maintain close proximity to data lines for compact layout while the segmented structure minimizes continuous coupling areas, thereby stabilizing the common voltage.
3Device complexity
If a conventional H-shaped common line is used, then the structure is simple and easy to fabricate, but bright-dark lines appear during display due to coupling-induced voltage drift
Solution Approach 1:
The common line is divided into multiple segments arranged in a meshed pattern, increasing structural complexity but significantly reducing capacitance coupling with data lines. This segmentation prevents voltage drift that causes bright-dark lines, thereby improving display uniformity while maintaining reasonable fabrication complexity.
Solution Approach 2:
The common line structure evolves from a two-dimensional H-shaped planar design to a three-dimensional meshed structure with segments distributed in multiple spatial dimensions. This dimensional transformation reduces coupling effects and eliminates display uniformity issues while the meshed pattern remains compatible with standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The meshed common line design effectively reduces parasitic capacitance, addressing the bright-dark lines issue and improving display quality by minimizing coupling effects.
Implementation Method 1
the capacitance coupling effect between a conventional H-shaped common line and the data lines is quite significant
Implementation Method 2
reducing the overlaying area and thus minimizing parasitic capacitance between data lines and the common line
Data Source
AI summary
An active device array substrate includes a substrate, first scan lines, second scan lines, data lines, display units and a meshed common line. The first and second scan lines are alternately arranged on the substrate. Each of the display units is respectively located between two adjacent data lines and respectively includes a first pixel and a second pixel, wherein the first pixel is electrically connected to one of the first scan lines, the second pixel is electrically connected to one of the second scan lines, and the first and second pixels are respectively electrically connected to a different data line. In addition, the meshed common line includes ring-shaped patterns, wherein each ring-shaped pattern includes two semi-ring-shaped patterns connected to each other and respectively located at both sides of a single data line, and the two semi-ring-shaped patterns of a same ring-shaped pattern are respectively located under different display units.