Partially Meshed Ground Plane for Capacitive Compensation
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Solution Overview
Problem
Interconnect channels in electronic devices suffer from capacitive parasitics that cause impedance mismatch and multi-reflection noise, particularly in short channels, leading to severe channel margin degradation, which current solutions attempt to address through complex receiver circuit designs and dynamic gain adjustments.
Innovation Solution
A capacitive compensation structure using a partially meshed ground plane is implemented, which reduces capacitive parasitics by increasing inductance and maintaining integrated crosstalk noise below a threshold, allowing for simpler receiver circuit designs and efficient silicon usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex receiver circuit designs with dynamic gain adjustments are used to address capacitive parasitics, then channel margin degradation is improved, but device complexity increases
Solution Approach 1:
The patent converts the harmful capacitive parasitics into a beneficial effect by introducing compensation capacitors that exploit the same capacitive phenomenon to cancel out the negative impacts of parasitic capacitance on the interconnect channel, thereby improving channel margin without complex receiver circuits
Solution Approach 2:
The patent introduces compensation capacitors as intermediary elements between the capacitive component and the interconnect channel. These capacitors act as mediators that offset the harmful effects of parasitic capacitance, providing a simpler solution compared to complex receiver circuit designs
2Reliability
If complex receiver circuit designs are implemented to compensate for capacitive parasitics, then channel performance is improved, but silicon die area increases
Solution Approach 1:
The patent converts the harmful capacitive parasitics into a beneficial effect by introducing compensation capacitors that exploit the same capacitive phenomenon to cancel out the negative impacts, thereby improving channel performance without requiring additional silicon die area for complex receiver circuits
Solution Approach 2:
The patent changes the capacitive parameters of the system by adding compensation capacitors with specific capacitance values that offset the parasitic capacitance. This parameter-based approach allows performance improvement through passive component adjustment rather than complex active circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates multi-reflection noise, enhances channel margins, and reduces silicon die area requirements, matching or exceeding the performance of more complex circuit designs while saving resources.
Implementation Method 1
capacitive parasitics that cause impedance mismatch and multi-reflection noise
Implementation Method 2
reduces capacitive parasitics by increasing inductance
Data Source
AI summary
Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.