Mesochronous DDR Interface Synchronization Under SoC Clock Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed data transfer between a system on a chip (SoC) and external DDR SDRAM is challenging due to tight timing requirements and jitter issues, especially when clock signals need to be distributed across long distances on the SoC, leading to difficulties in meeting clock and data strobe timing requirements.
Innovation Solution
A memory interface with a cleanup phase-locked loop (PLL) and synchronization circuit that generates a clean clock signal from a reference clock, reduces jitter, and synchronizes data using this clean clock, thereby improving data transfer accuracy and meeting timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock signals are distributed across long distances on the SoC, then data transfer capability is improved, but jitter increases and timing requirements cannot be met
Solution Approach 1:
The system segments the clock distribution function by placing separate cleanup PLLs in different PHY blocks rather than using a single centralized clock source. Each PHY block independently generates its own clean clock signal, eliminating the need for long-distance clock signal distribution and the associated jitter problems while maintaining high data transfer speeds.
2Productivity
If data is transferred at high speed, then productivity is improved, but synchronization accuracy deteriorates due to jitter
Solution Approach 1:
The cleanup PLL performs preliminary cleaning of the clock signal before data transfer operations begin. By pre-generating a clean, stable clock signal with reduced jitter in each PHY block, the system ensures that high-speed data transfer can proceed with maintained synchronization accuracy without being degraded by jitter accumulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces jitter and ensures accurate data transfer by generating a clean clock signal that meets the stringent timing requirements for high-speed data transfer across the SoC, improving the reliability of data synchronization and reducing latency.
Implementation Method 1
a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal
Implementation Method 2
the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal
Data Source
AI summary
In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.