Mesochronous Digital Interface Without FIFO Buffer Overhead
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Solution Overview
Problem
Efficient communication between subsystems of a system-on-a-chip (SoC) is challenging due to mesochronous clock signals with unknown phase differences, leading to potential data transmission delays and failures.
Innovation Solution
The system adjusts the phase of the transmitting clock signal relative to the receiving clock signal to ensure synchronized data transfer without the need for intervening circuits like FIFO buffers, thereby eliminating hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FIFO buffer is used to ensure safe data transmission between subsystems with mesochronous clock signals, then data transmission reliability is improved, but hardware area consumption increases
Solution Approach 1:
The patent extracts and eliminates the FIFO buffer component from the system by implementing phase-aligned clock signaling. The transmitting subsystem determines the phase of its clock signal relative to the receiving subsystem's clock signal and adjusts data transmission timing accordingly, removing the need for intermediate buffering hardware and reducing area consumption while maintaining transmission reliability.
Solution Approach 2:
The patent introduces phase information as an intermediary mechanism between transmitting and receiving subsystems. By determining and communicating clock phase relationships, the system enables direct synchronized data transfer without requiring physical FIFO buffers, thus mediating the timing coordination through signal phase alignment rather than hardware intermediaries.
2Reliability
If a FIFO buffer is used to manage data transmission between subsystems with different clock phases, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming FIFO buffer hardware by implementing phase-based clock synchronization. The transmitting subsystem determines the phase relationship between its clock and the receiving subsystem's clock, then transmits data at optimally timed intervals, eliminating the continuous power consumption associated with FIFO buffer operation while ensuring reliable data transfer.
Solution Approach 2:
The system uses its own clock signals and phase detection capabilities to self-coordinate data transmission timing. The transmitting subsystem autonomously determines phase relationships and adjusts transmission timing without requiring external buffering or complex power-managed intermediate structures, reducing overall power consumption while maintaining reliability.
3Area of stationary object
If phase detection and clock alignment are implemented between subsystems, then hardware overhead is reduced by eliminating FIFO buffers, but system complexity increases
Solution Approach 1:
The patent implements a universal phase detection and clock alignment mechanism that can be applied to any pair of subsystems within the integrated circuit. This multi-functional approach allows the same phase determination logic to serve multiple communication channels, reducing overall hardware overhead while managing complexity through reuse rather than duplication of components.
Solution Approach 2:
The system implements feedback through phase detection where the transmitting subsystem determines the phase relationship between its clock signal and the receiving subsystem's clock signal, then uses this phase information to adjust transmission timing. This feedback mechanism enables automatic adaptation to phase differences without requiring complex hardwired timing logic, reducing hardware overhead while managing complexity through adaptive control.
Data Source
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AI summary
An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.