Full-Duplex Mesochronous Link Flow Control for NoC
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Solution Overview
Problem
Existing communication techniques for mesochronous on-chip communication lack standard implementation and effective flow-control management, leading to limitations in building full-duplex links that can guarantee maximum throughput, low latency, and reduced area, especially in Network on Chip (NoC) architectures with multiple clock domains.
Innovation Solution
A method and system architecture that implement full-duplex mesochronous links using the Globally Asynchronous Locally Synchronous (GALS) approach, combining Network on Chip (NoC) paradigm with SKew Insensitive Link (SKIL) mechanism to manage req-ack flow control, allowing communication between synchronous units with arbitrary clock skew, and reducing wire-delay effects to achieve high throughput and low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional mesochronous communication techniques are used, then communication between clock domains is enabled, but standard-cell technology cannot be used and implementation complexity increases
Solution Approach 1:
The patent introduces a mesochronous communication interface as an intermediary component that enables standard-cell based implementation of mesochronous communication. This interface acts as a mediator between clock domains, providing standardized capture and drive logic that can be implemented using conventional standard-cell libraries, thus resolving the contradiction between communication capability and ease of manufacture.
2Productivity
If full-duplex mesochronous links are implemented, then maximum throughput is achieved, but flow-control management complexity increases
Solution Approach 1:
The patent segments the flow-control management functionality into distinct components: a send side controller that manages data transmission and an acknowledge controller that handles acknowledgment signals. This segmentation allows each component to be optimized independently, reducing overall complexity while maintaining full-duplex throughput capability.
Solution Approach 2:
The patent implements a feedback mechanism where acknowledgment signals are sent back from the receive side to the send side, enabling automatic flow-control management. This feedback loop allows the system to dynamically adjust data transmission based on buffer status, achieving maximum throughput without complex manual intervention.
3Use of energy by stationary object
If clock skew constraints are relaxed, then clock tree simplification and power reduction are achieved, but timing verification reliability decreases
Solution Approach 1:
The patent performs preliminary synchronization of data and clock signals at the mesochronous communication interface before data capture. By establishing proper timing relationships in advance through synchronization logic, the system can operate with relaxed clock skew constraints without compromising timing verification reliability, thus reducing power consumption while maintaining verification confidence.
Data Source
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AI summary
Data transport is provided in a communication network such as a Network-on-Chip (NoC) arrangement via full-duplex mesochronous links (19, 29) between routers (R). Request signals and response signals are exchanged between these routers acting alternatively as an initiator (10) and a target (20) operating in respective clock domains at opposite ends of respective full-duplex mesochronous links (19, 29). The request initiator flow control signals (init_req and init ack) are monitored at the target (20) end of the link (19, 29) while the response target flow control signals (targ_r_req and targ_r_gnt) are monitored at the initiator (10) end of the link (19, 29). The monitoring action involves ascertaining if a request has been granted at the initiator (10) end of the link (19, 29) and if a response has been granted at the target (20) end of said link (19, 29) thus correspondingly managing the data flow over the link.