Mesosynchronous Data Bus Timing Management
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Solution Overview
Problem
In high-speed data transmission across computer bus systems, phase relationships of data bits can vary significantly, leading to errors and requiring de-skewing and phase alignment at each memory node, which complicates device design and increases power consumption.
Innovation Solution
An interconnection system where a first clock is provided to nodes, and a second clock is generated with a time delay offset to maintain constant bit transmission time, using a clock data recovery circuit and phase alignment buffer to synchronize serial data with the internal clock, and a switch to route data between external and internal ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted at high speed across the bus, then transmission bandwidth is improved, but phase relationship variations increase causing errors
Solution Approach 1:
The patent implements dynamic phase alignment by allowing the phase relationship between data bits and system clock to vary adaptively across different bus lines. Instead of enforcing a fixed synchronous relationship, the system dynamically adjusts to accommodate propagation time differences, enabling high-speed transmission while maintaining data integrity through flexible phase management.
Solution Approach 2:
The patent changes the timing parameter of data transmission by allowing data bits to be transmitted at different phases relative to the system clock on different bus lines. This parameter change accommodates varying propagation delays without requiring uniform timing across all lines, thus maintaining reliability at high speeds.
2Reliability
If de-skewing and phase alignment are performed at each memory node, then data accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the phase alignment function into the overall system timing architecture rather than implementing separate de-skewing circuits at each node. By combining timing management at the system level and utilizing the natural phase relationships established by the clock distribution network, the patent eliminates the need for complex individual node circuits while maintaining data accuracy.
Solution Approach 2:
The patent enables each memory node to self-align to the phase relationship naturally established by the propagated clock signal and transmitted data. Instead of requiring active de-skewing circuits, each node automatically adapts to its specific phase relationship, simplifying node design while maintaining synchronization accuracy.
3Reliability
If de-skewing and phase alignment circuits are implemented at each node, then data accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts the complex de-skewing and phase alignment functions from individual memory nodes and relocates timing management to the system level through the clock distribution network. By removing these functions from each node, the patent significantly reduces per-node power consumption while maintaining data transmission accuracy through the centralized timing architecture.
4Reliability
If clock is transmitted with data on each line, then synchronization is improved, but transmission overhead increases
Solution Approach 1:
The patent makes the system clock serve multiple functions: it provides timing reference for data transmission, enables phase relationship establishment, and facilitates synchronization across all bus lines simultaneously. By using the same clock signal for multiple purposes rather than transmitting separate clock signals with each data line, the patent reduces transmission overhead while maintaining synchronization.
Data Source
AI summary
A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.