Message-Based Memory Access for Multi-Core Bandwidth Efficiency
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Solution Overview
Problem
Conventional synchronous memory systems face limitations in multi-core processors due to fixed memory access delays and granularities, leading to inefficient bandwidth utilization and increased protocol overhead, especially when dealing with irregular data access patterns.
Innovation Solution
A message-based memory access system that replaces synchronous bus transactions with asynchronous and concurrent request and response messages, allowing for variable memory access lengths, priorities, and flexible scheduling, enabling improved CPU memory channel utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed data granularity is used for memory access, then transmission efficiency is improved, but bandwidth utilization deteriorates due to waste in irregular access patterns
Solution Approach 1:
The patent implements variable data granularity in memory access operations, allowing the system to dynamically adjust the amount of data transmitted based on actual access needs. This resolves the contradiction by making the data transmission flexible rather than fixed, enabling efficient handling of both regular and irregular access patterns without wasting bandwidth.
Solution Approach 2:
The system changes the parameter of data granularity from a fixed value to a variable that can be adjusted according to access patterns. By allowing the data length parameter to vary, the system maintains high transmission efficiency for large data accesses while avoiding bandwidth waste for small, irregular accesses.
2Device complexity
If synchronous access protocol is used, then timing control is simplified, but adaptability deteriorates due to fixed delay requirements
Solution Approach 1:
The patent introduces asynchronous memory access mechanisms that allow variable delays and flexible timing, moving away from rigid synchronous protocols. This enables the system to adapt to different access patterns and workloads while maintaining manageable timing control through software or buffer-based coordination.
Solution Approach 2:
The system changes the timing parameter from fixed (synchronous) to variable (asynchronous), allowing memory access delays to be adjusted based on actual needs. This improves adaptability for different access patterns while managing complexity through buffer management and coordination protocols.
3Productivity
If large data granularity is used, then fewer memory transactions are required, but protocol overhead increases when data needs to be divided
Solution Approach 1:
The patent implements dynamic data granularity adjustment, allowing the system to select appropriate data sizes for each memory transaction based on actual access requirements. This reduces the number of transactions needed for large data accesses while avoiding the protocol overhead of dividing small accesses into multiple transactions, as each transaction can be optimally sized.
Solution Approach 2:
The system changes the data granularity parameter from fixed to variable, enabling optimal transaction sizing. When large data needs to be accessed, larger granularity reduces transaction count; when small data is accessed, smaller granularity avoids unnecessary division and protocol overhead.
Data Source
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AI summary
A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.