Message-Based Processor Cores With Cyclic Addressing to Reduce Bandwidth
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Solution Overview
Problem
Message-based processor systems face high bandwidth requirements due to the need for high connectivity in neural networks, particularly in fully connected layers, which strain the message exchange facility.
Innovation Solution
A message-based processor system with a processor element controller that utilizes a cyclic set of address computation modes to efficiently update processor elements based on pattern information, reducing message size and bandwidth demands by dynamically computing addresses and updating states in a subset of processor elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a neural network layer is fully connected to the preceding layer, then the neural network achieves high connectivity and computational accuracy, but the bandwidth requirement of the message exchange facility increases significantly
Solution Approach 1:
The patent segments the fully connected neural network layer into multiple processing cycles. Instead of updating all processor elements simultaneously requiring high bandwidth, the system divides the update operation into segments processed sequentially or in smaller batches, reducing the peak bandwidth requirement while maintaining the same computational result.
Solution Approach 2:
The patent implements periodic action by cycling through different subsets of processor elements in successive time periods. The processor element controller updates processor elements in a systematic sequence across multiple cycles, allowing the message exchange facility to handle lower bandwidth loads periodically rather than requiring sustained high bandwidth for all connections simultaneously.
2Productivity
If the processor element controller updates all processor elements simultaneously, then the processing speed is maximized, but the message size and bandwidth requirements increase
Solution Approach 1:
The patent segments the set of processor elements into multiple subsets that are updated in different time periods. The processor element controller manages these subsets systematically, updating one subset at a time with compact messages that specify only the current subset's parameters, thereby reducing message size while maintaining overall processing throughput through multiple cycles.
3Measurement precision
If the system uses detailed address specifications for each processor element, then the addressing precision is maximized, but the message size increases
Solution Approach 1:
The patent segments the addressing information by specifying processor elements in terms of subset parameters rather than individual detailed addresses. The message contains compact specifications such as starting address, number of elements, and stride values that define subsets of processor elements, achieving sufficient addressing precision with much smaller message sizes compared to listing each processor element address individually.
Data Source
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AI summary
A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.