Message-Type Memory Module Error Correction via SCBC Segmentation
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Solution Overview
Problem
Current memory systems face challenges in providing high reliability and low power consumption, especially with increasing memory configurations, as existing error correction methods like ECC and Chipkill are inflexible and inefficient, particularly when dealing with multi-bit errors and varying data access granularities.
Innovation Solution
The proposed solution involves a memory access method and apparatus for a message-type memory module using (M+2) dynamic random access memories (DRAMs), where data is stored in single chip burst clusters (SCBCs), with error detecting and correcting codes calculated and distributed across DRAMs to enable fine-granularity encoding protection and variable-granularity memory access, allowing for error correction in any single DRAM with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Chipkill memory technology is used to achieve high reliability through wider MC bit width and data encoding at coarser granularity, then error tolerance is improved, but adaptability deteriorates because it can only be applied to DRAM chips with fixed 4-bit bit width
Solution Approach 1:
The invention segments the error correction mechanism into fine-granularity units (per SCBC rather than per chip), allowing the system to adapt to different DRAM chip configurations while maintaining error tolerance. Each SCBC is independently protected with error detecting and correcting codes, enabling flexible deployment across various chip architectures.
Solution Approach 2:
The invention introduces dynamic granularity adjustment capability, allowing the memory system to adapt error correction to different access patterns and data granularities. The system can dynamically select between fine-granularity SCBC-level protection and coarser-granularity protection based on actual access requirements, providing both high reliability and adaptability.
2Reliability
If data encoding at extremely coarse granularity is used in Chipkill technology, then error correction capability is improved, but power consumption increases because data read by DIMM each time is much larger than data requested by actual memory access request
Solution Approach 1:
The invention applies partial action by performing error correction only on the specific SCBC that contains the error, rather than correcting entire chips or large data blocks. When an error is detected in one SCBC, only that SCBC is re-read and corrected, minimizing the amount of data transferred and processed, thus reducing power consumption while maintaining error correction capability.
Solution Approach 2:
The invention changes the granularity parameter of error correction from coarse (chip-level) to fine (SCBC-level). This parameter change allows the system to correct errors at the smallest necessary unit, reducing the volume of data that needs to be read, processed, and rewritten, thereby significantly reducing power consumption during error correction operations.
3Ease of manufacture
If ECC memory is used to perform data protection in basic unit of memory module bit width, then implementation simplicity is improved, but error correction capability deteriorates because multi-bit errors cannot be corrected
Solution Approach 1:
The invention segments the memory protection unit into smaller SCBC units within each DRAM chip. By calculating error detecting and correcting codes for each SCBC individually and storing them in dedicated locations, the system achieves multi-bit error correction capability while maintaining implementation simplicity through standardized encoding processes at the SCBC level.
Solution Approach 2:
The invention adds a new dimension to error correction by introducing dedicated error code storage locations within the memory module structure. Error detecting codes are stored in one DRAM and error correcting codes in another, creating a multi-dimensional protection scheme that enables sophisticated error correction without complicating the basic encoding process.
Data Source
AI summary
A memory access apparatus includes a read-write module and a processing module. The read-write module is configured to store an error detecting code in an (M+2)th DRAM in the memory row, and store the error correcting code in a Zth DRAM in the memory row, where Z is a positive integer, 1≦Z≦(M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs. The processing module is configured to calculate one group of error detecting code for each single chip burst cluster (SCBC) in a memory row, and calculate one group of error correcting code for all SCBCs in a memory row.