Meta Interface for Host Bus Translation in Complex ASICs
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Solution Overview
Problem
Existing input/output devices in computer systems face complexity and inefficiency when designed to work with multiple system buses, requiring specific logic for each bus type and separate verification strategies for different architectures, leading to increased design complexity and verification time.
Innovation Solution
A meta interface is introduced to electrically couple input/output devices to multiple host system buses without altering the device configuration, allowing the device's functionality to be independent of the host bus, and enabling end-to-end verification of complex ASICs across various configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a device is configured to work with multiple system buses by including logic for each bus type, then the device's adaptability is improved, but the device complexity increases and becomes too complex and inefficient
Solution Approach 1:
The patent introduces a bus interface layer as an intermediary component that sits between the device and multiple system buses. This interface layer contains the bus-specific logic for tracking transactions and handling bus protocols, while the device itself remains generic and bus-agnostic. The interface translates device operations into bus-specific transactions, allowing the device to work with multiple bus types without incorporating bus-specific logic directly into the device.
Solution Approach 2:
The patent segments the system into two distinct parts: the device (which generates high-level read/write operations) and the bus interface (which handles bus-specific transaction tracking and protocol conversion). This segmentation allows the device to remain simple and generic while the interface handles the complexity of multiple bus types. Each bus interface can be independently configured for different bus types without affecting the device.
2Reliability
If separate verification strategies are implemented for each system bus architecture, then the verification accuracy for each architecture is improved, but the verification time and complexity increase substantially
Solution Approach 1:
The patent creates a universal verification strategy that works across multiple bus architectures by verifying the bus interface layer independently of the specific bus type. The verification process focuses on the generic device operations and the interface's ability to translate them into bus-specific transactions. This universal approach allows the same verification methodology to be applied to different bus types (PCIe, HT, JBus, etc.) without requiring separate verification strategies for each architecture.
Data Source
AI summary
An interface is provided to couple an input/output device (e.g., a network interface unit) to one or more different host system buses without altering the configuration of the device (e.g., to include logic specific to the host buses). Functionality of the device (e.g., MTU size, error detection) is therefore independent of the host bus. Host bus logic for managing operation of the host bus is augmented with logic for translating between semantics of the interface and the host bus. Also, end-to-end verification of a complex ASIC in multiple configurations or environments can be performed over the interface without probing into the ASIC.