Granular Single-Pass Metadata Access in Memory Column Planes
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in accessing error correction information and metadata without impacting performance by increasing the physical size of the memory array, and there is a need to protect non-accessed bit lines during write operations.
Innovation Solution
Implementing granular single-pass metadata access operations using a memory device with a plurality of column planes, where data and additional information are stored in selected and non-selected portions, and using write enable signals to protect non-accessed bit lines, with metadata stored in an extra column plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metadata and error correction information are stored in the memory array along with data, then information storage capability is improved, but access performance deteriorates due to increased access time
Solution Approach 1:
The memory array is segmented into multiple column planes, with specific column planes designated for storing metadata and error correction information separately from data. This segmentation allows independent access to different types of information, enabling metadata and error correction to be retrieved without accessing the entire memory array, thus improving access performance while maintaining enhanced storage capability.
Solution Approach 2:
Metadata and error correction information are pre-positioned in dedicated column planes during memory initialization or data write operations. This preliminary placement ensures that when data access is required, the associated metadata and error correction information are already in optimal locations for simultaneous or near-simultaneous retrieval, eliminating additional access time penalties.
2Quantity of substance
If the physical size of the memory array is increased to store additional information, then storage capacity is improved, but device complexity and access performance deteriorate
Solution Approach 1:
The memory device utilizes existing column plane infrastructure for multiple purposes: data storage in primary column planes and metadata/error correction information storage in dedicated column planes. This multi-functionality approach allows the memory array to handle both data and auxiliary information without requiring separate physical memory structures, thereby increasing storage capacity while avoiding proportional increases in device complexity.
Solution Approach 2:
Instead of expanding storage capacity by increasing the size of individual column planes (one-dimensional expansion), the invention adds another dimension by introducing dedicated column planes for metadata and error correction. This dimensional approach to organizing information allows the memory device to store additional information types without significantly increasing the physical footprint or complexity of the core memory array structure.
3Productivity
If all bit lines are accessed during write operations, then write speed is improved, but non-accessed bit lines are vulnerable to disturbances
Solution Approach 1:
Write enable signals are applied selectively to specific column planes based on the type of information being written. When writing metadata or error correction information to dedicated column planes, write enable signals are localized to those specific planes rather than activating all bit lines. This local quality approach maintains write speed for targeted operations while protecting non-accessed bit lines from disturbances by keeping them in a high-impedance state.
Data Source
AI summary
Apparatuses, systems, and methods for separate write enable signals for granular single pass metadata access operations. During an example write operation a memory may receive data bits and at least one metadata bit. A set of bit lines in a first column plane is selected and a first write enable signal is provided which enables writing data to each of that set of bit lines. A second set of bit lines in a second column plane is selected and a second write enable signal is provided which enables writing the at least one metadata bit to a selected subset of the second set of bit lines.