Metadata Cache Circuit for Higher Memory Bandwidth

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Solution Overview

Problem

Existing memory systems require separate transactions for user-data and metadata storage, leading to inefficient utilization of external memory and reduced bandwidth.

Innovation Solution

Implementing a metadata cache within the memory control device to bifurcate user-data and metadata storage, allowing concurrent retrieval and storage operations, reducing the need for separate external memory transactions and optimizing bandwidth usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate transactions are used for user-data and metadata storage, then storage functionality is maintained, but external memory utilization increases and bandwidth decreases

Engineering Contradiction:
Improvememory bandwidthVSAvoidexternal memory utilization
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the memory storage function by creating a dedicated metadata cache within the memory control device that separately stores metadata components, while user data is stored in external memory. This segmentation allows concurrent operations: metadata can be retrieved from the local cache while user data is being transferred to or from external memory, eliminating the sequential transaction overhead and improving bandwidth utilization without increasing external memory usage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The metadata cache acts as an intermediary between the memory control device and external memory for metadata storage. Instead of directly writing metadata to external memory through separate transactions, the system uses the local metadata cache as a buffer and intermediary storage location, enabling more efficient data flow and reducing the frequency of external memory accesses.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If metadata is explicitly stored in cache, then access performance improves, but cache size and power consumption increase

Engineering Contradiction:
Improvemetadata access performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by selectively storing only non-default metadata values in the cache rather than all metadata values. The system infers that metadata not explicitly stored must be default values, allowing the cache to be smaller and consume less power while maintaining performance for the subset of metadata that actually varies. This partial caching strategy reduces energy consumption while preserving access performance for critical non-default metadata.

Inventive Principle:
Principle #16Partial or excessive action

3Use of energy by moving object

If metadata cache size is reduced, then power consumption decreases, but cache miss rate increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcache hit rate
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the parameter of metadata storage by introducing inferential storage semantics where the cache stores only non-default metadata values. This parameter change fundamentally alters how the cache operates: instead of storing all metadata and relying on high hit rates, the system stores a selective subset and uses inference to handle misses. This transforms the performance-power tradeoff by reducing power consumption through smaller cache size while maintaining acceptable performance through intelligent inference rather than brute-force caching.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250370930A1Metadata-caching integrated circuit device
Publication Date: 2025.12.04 ASTERA LABS INC
  • US20250370930A1 patent drawing
  • US20250370930A1 patent drawing
  • US20250370930A1 patent drawing

AI summary

A memory control device implements split storage of user-data and metadata components of a compound write data word, outputting the user-data component via a memory control interface for storage within an external memory subsystem while separately storing the metadata component within a metadata cache implemented within the memory control device.