Metadata-Caching Memory Controller Bifurcates Storage
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Solution Overview
Problem
Current data processing systems require separate write transactions to external memory for user-data and metadata components, leading to inefficient memory utilization and bandwidth usage, and lack an effective method to manage metadata storage efficiently.
Innovation Solution
Implementing a metadata cache within the memory control device that bifurcates storage of user-data and metadata components, allowing in-situ metadata storage and reducing external memory transactions, with the option to infer default metadata values to minimize cache size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate write transactions are used for user-data and metadata to external memory, then data integrity is maintained, but memory utilization efficiency deteriorates and bandwidth is wasted
Solution Approach 1:
The patent segments the write transaction into two independent parts: user-data write to external memory and metadata write to on-die cache. This segmentation allows the two data types to be handled separately, enabling metadata to be cached locally while user-data goes to external memory, thereby reducing the number of external memory transactions and improving memory utilization efficiency.
Solution Approach 2:
The patent introduces a new storage dimension by adding on-die cache memory within the memory control device, separate from the external memory system. This dimensional change allows metadata to be stored in a different location (on-die cache) from user-data (external memory), enabling parallel access paths and reducing external memory transaction overhead.
2Productivity
If metadata is stored in on-die cache instead of external memory, then memory bandwidth availability increases, but cache size requirements increase power consumption
Solution Approach 1:
The patent applies local quality by making the on-die cache associative rather than direct-mapped, allowing different cache lines to be accessed simultaneously based on their tag matches. This local quality improvement enables selective caching of metadata that is actually needed, reducing unnecessary cache power consumption while maintaining high bandwidth availability for accessed metadata.
Solution Approach 2:
The patent uses partial action by implementing an associative cache that only stores and retrieves metadata entries that are actually needed, rather than caching all possible metadata. The cache selectively holds only relevant metadata entries, reducing power consumption while maintaining the bandwidth benefits of local caching for the subset of metadata that is frequently accessed.
3Speed
If all metadata values are explicitly stored in cache, then metadata access speed increases, but cache size and power consumption increase
Solution Approach 1:
The patent extracts only the necessary metadata entries from the set of all possible metadata and stores them in the on-die cache. By using associative caching, the system extracts and stores only those metadata entries that are actually needed for current operations, rather than storing all possible metadata values, thereby reducing cache size and power consumption while maintaining fast access speed for the extracted subset.
Solution Approach 2:
The patent changes the cache organization parameter from direct-mapped to associative, which fundamentally alters how metadata is stored and accessed. This parameter change enables the cache to hold multiple valid entries simultaneously and select the correct one based on tag matching, allowing the cache to be smaller while still providing fast access to the specific metadata entries that are actually needed.
Data Source
AI summary
A memory control device implements split storage of user-data and metadata components of a compound write data word, outputting the user-data component via a memory control interface for storage within an external memory subsystem while separately storing the metadata component within a metadata cache implemented within the memory control device.