Metal Air Gap Formation in Semiconductor Interconnects
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce interconnect capacitance between copper lines in integrated circuits, which is exacerbated by the difficulty in forming air gaps using traditional processes that often collapse delicate patterns and require exposure to liquid etchants, leading to integration issues and increased signal delay.
Innovation Solution
A method involving a sacrificial patterned dielectric layer to form copper gapfill lines between adjacent lines on a substrate, using physical vapor deposition and a remote fluorine etch process to redistribute copper without breaking vacuum, followed by a conformal capping layer to protect the copper from oxidation, enabling the creation of air gaps without exposing the substrate to atmosphere.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional liquid etch processes are used to form air gaps, then the air gaps can be created, but the delicate patterns collapse and integration issues arise
Solution Approach 1:
The patent performs all air gap formation processes in a vacuum environment without breaking vacuum, using plasma-based etching and deposition techniques. This inert atmosphere prevents pattern collapse and maintains structural integrity throughout the multi-step process of forming sacrificial patterns, depositing copper, and removing sacrificial material.
Solution Approach 2:
The patent replaces traditional liquid etch processes with plasma-based remote etching techniques. This substitution eliminates the mechanical and chemical issues associated with liquid etchants, allowing for precise air gap formation without pattern collapse while maintaining vacuum conditions throughout the process.
2Reliability
If copper lines are used to decrease signal loss, then conductivity improves, but interconnect capacitance increases causing signal delay
Solution Approach 1:
The patent extracts the dielectric material between copper lines to create air gaps, removing the capacitive coupling between adjacent conductors. This extraction reduces interconnect capacitance and signal delay while preserving the low-resistivity copper interconnect structure, directly addressing the time delay issue without sacrificing conductivity.
3Ease of manufacture
If air gaps are formed using processes that require breaking vacuum, then the substrate can be processed, but integration issues and yield loss occur
Solution Approach 1:
The patent maintains continuous vacuum conditions throughout the entire air gap formation process, including sacrificial pattern deposition, copper filling, and sacrificial material removal. This continuous vacuum operation eliminates the need to break and re-establish vacuum, preventing yield loss and maintaining high manufacturing efficiency while enabling complete substrate processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces interconnect capacitance by forming reliable air gaps between copper lines, enhancing signal frequency and reducing signal delay while maintaining high conductivity and yield, and is compatible with vacuum-based substrate processing systems, avoiding the limitations of liquid etch processes.
Implementation Method 1
forming a nonconformal layer of copper by physical vapor deposition onto the conformal titanium barrier layer
Implementation Method 2
etching the conformal titanium barrier layer from the tops of the two adjacent lines of silicon oxide by introducing radical-fluorine from a first remote plasma region
Implementation Method 3
etching the two adjacent lines of silicon oxide by introducing radical-fluorine from a remote plasma region
Implementation Method 4
depositing a conformal capping layer over the patterned substrate to protect the copper gapfill line from oxidation
Data Source
AI summary
Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The air gaps may be located between copper lines on the same layer. A sacrificial patterned dielectric layer is used as a template to form a layer of copper by physical vapor deposition in a substrate processing system (i.e. a mainframe). Without breaking vacuum, the copper is redistributed into the gaps with a copper reflow process. Dielectric material from the template is removed, again in the same mainframe, using a remote fluorine etch process leaving the gapfill copper as the structural material. A conformal capping layer (such as silicon carbon nitride) is then deposited (e.g. by ALD) to seal the patterned substrate before removing the patterned substrate from the mainframe.