Metal Alloy Layer on Elevated Source Drain for Low Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in reducing operating current consumption while maintaining effective current control and suppressing short channel effects, particularly in multi-gate transistors where current control capability is limited by the resistance of elevated source/drain structures.
Innovation Solution
The semiconductor device incorporates a first fin on a substrate with a gate electrode intersecting the fin, an elevated source/drain on the side of the gate, and a metal alloy layer on the upper surface and sidewall of the elevated source/drain, with the metal alloy layer being in direct contact with the fin and a contact, reducing current resistance and consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistors with elevated source/drain structures are used to suppress short channel effects, then short channel effect suppression is improved, but operating current consumption increases due to high resistance in the elevated source/drain
Solution Approach 1:
The patent applies composite materials by forming a metal alloy layer (such as cobalt silicide or nickel silicide) on the elevated source/drain structure. This creates a composite system where the semiconductor fin provides the multi-gate channel for SCE suppression, while the metal alloy layer provides low-resistance current paths, thereby resolving the contradiction between reliability and energy consumption.
Solution Approach 2:
The patent segments the current path into two distinct routes: one through the elevated source/drain (for vertical current flow) and another through the metal alloy layer (for lateral current flow). This segmentation allows the device to utilize the advantages of both paths, reducing overall resistance while maintaining the multi-gate structure for SCE suppression.
2Reliability
If the gate length is increased to improve current control capability, then current control is improved, but device scaling is limited
Solution Approach 1:
The patent changes the resistance parameter of the source/drain region by introducing a low-resistance metal alloy layer. This parameter change improves current control capability without requiring an increase in gate length, enabling better performance in scaled devices where gate length reduction is necessary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly lowers operating current consumption by allowing current to flow mainly through the contact and metal alloy layer, which has lower resistance than the elevated source/drain, thereby enhancing current control and reducing power usage.
Implementation Method 1
a metal alloy layer on an exterior surface of the elevated source/drain that provides a primary electrical path between the fin and the contact
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.