Metal Barrier Layer for CMOS-MEMS Release Chemical Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated CMOS-MEMS devices face damage due to exposure to hydrofluoric acid-based chemical etchants during the release process, as the CMOS wafer's silicon oxide in inter-metal dielectrics and passivation stack etches rapidly, making it unsuitable for HF exposure.
Innovation Solution
A metal barrier layer is deposited on the sidewalls of passivation openings in the CMOS wafer to protect the dielectric layer from release chemicals, using metals like Titanium, Titanium Nitride, or Aluminum that are resistant to HF, preventing exposure and damage during the MEMS structure release.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If HF-based chemical etchant is used to release MEMS structure, then MEMS sacrificial layer is effectively removed, but CMOS wafer dielectric layer is damaged due to rapid etching
Solution Approach 1:
A metal barrier layer (titanium, titanium nitride, or aluminum) is deposited on the sidewalls of passivation openings to act as an intermediary protective layer. This barrier layer selectively prevents HF-based chemical etchants from attacking the CMOS wafer dielectric layer while allowing the etchants to effectively remove the MEMS sacrificial layer, thus resolving the contradiction between MEMS release efficiency and CMOS wafer integrity
Solution Approach 2:
The protective metal barrier layer is applied locally only on the sidewalls of passivation openings where the dielectric layer is exposed, rather than coating the entire wafer. This localized application provides targeted protection to vulnerable areas while maintaining the overall effectiveness of the HF-based release process for the MEMS structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The metal barrier layer effectively prevents the CMOS wafer from reacting with the release chemical, ensuring the integrity of the CMOS layers and enabling the successful fabrication of integrated CMOS-MEMS devices without damage from HF exposure.
Implementation Method 1
a metallic barrier layer is deposited on the sidewall that prohibits exposure of the dielectric layer to a release chemical employable to release the MEMS structure
Implementation Method 2
a metallic barrier layer is deposited on the sidewall
Data Source
AI summary
Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.