Metal Bitline Formation for Low-Resistance 3D Stacked Memory
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Solution Overview
Problem
Current memory technologies face challenges in creating buried bitlines (BLs) that meet performance requirements, particularly in three-dimensional integration, where reducing interconnect wire length and power consumption are essential.
Innovation Solution
The creation of metal bitlines on the bottom surface of wafers using techniques such as salicide and damascene processes, which involve patterning trenches, depositing metal layers, and forming low-resistance transition metal silicides, along with wafer thinning and bonding processes to form three-dimensional memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If diffused bitlines are used in three-dimensional memory structures, then the memory can be stacked vertically with reduced interconnect wire length, but the resistance of the bitlines increases and performance requirements are not met
Solution Approach 1:
The patent changes the material parameter of the bitline from diffused silicon to metal (such as copper, aluminum, or tungsten), which fundamentally alters the electrical resistance characteristic. This material substitution enables the bitline to meet performance requirements while maintaining the three-dimensional stacked structure with reduced interconnect length.
Solution Approach 2:
The patent employs metal materials with superior electrical conductivity properties to replace traditional diffused bitlines. The metal bitlines provide both the low resistance required for high performance and the structural integrity needed for three-dimensional integration, effectively combining the benefits of vertical stacking with excellent electrical characteristics.
2Reliability
If metal bitlines are created using salicide or damascene processes, then resistance is reduced and conductivity is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent divides the bitline formation process into distinct stages: first creating the metal layer through deposition (salicide or damascene), then performing wafer thinning to expose the metal bitline, and finally bonding wafers to form the three-dimensional structure. This segmentation allows each process step to be optimized independently, managing overall complexity while achieving low-resistance metal bitlines.
3Volume of moving object
If wafer thinning and bonding processes are used to form three-dimensional memory structures, then space utilization is improved and interconnect length is reduced, but the manufacturing difficulty increases
Solution Approach 1:
The patent performs wafer thinning and metal bitline formation on individual wafers before stacking and bonding them together to form the three-dimensional memory structure. This preliminary preparation of each wafer independently simplifies the overall manufacturing process by breaking down the complex three-dimensional fabrication into manageable two-dimensional steps that can be executed and quality-checked at each stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and enhances performance by utilizing metal bitlines, allowing for better conductivity and reduced power consumption in three-dimensional memory devices.
Implementation Method 1
depositing metal layers
Implementation Method 2
forming low-resistance transition metal silicides
Implementation Method 3
depositing metal layers
Implementation Method 4
wafer bonding processes to form three-dimensional memory structures
Data Source
AI summary
Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.