Metal Bitline Structure for Low-Resistance 3D Stacked Memory
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Solution Overview
Problem
Existing memory technologies face challenges in creating buried bitlines (BLs) that meet performance requirements, especially in three-dimensional (3D) integration where space utilization and interconnect efficiency are critical.
Innovation Solution
The creation of metal bitlines (BLs) on the bottom surface of a wafer using techniques such as the salicide process or damascene process, which reduces resistance and enhances performance by stacking and bonding multiple wafers to form 3D memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional non-metal buried bitlines are used in 3D memory structures, then manufacturing simplicity is maintained, but resistance is high and performance is insufficient
Solution Approach 1:
The bitline structure is segmented into multiple components: a base layer formed in the substrate, and a metal layer deposited on top of the base layer. This segmentation allows each layer to be optimized independently - the base layer provides structural integration while the metal layer provides low resistance, resolving the contradiction between manufacturing simplicity and performance.
Solution Approach 2:
The patent employs composite material structure by combining a base layer (silicon or silicon-germanium) with a metal layer (tungsten, cobalt, or copper). This composite approach leverages the advantages of both materials: the semiconductor base layer integrates well with existing CMOS processes while the metal layer provides superior electrical conductivity, thereby improving performance without excessive manufacturing complexity.
2Reliability
If metal bitlines are implemented using salicide or damascene processes, then resistance is reduced and performance is improved, but manufacturing complexity increases
Solution Approach 1:
The base layer is formed in the substrate before the metal layer is deposited. This preliminary action prepares the substrate with a suitable foundation that facilitates subsequent metal deposition and reduces resistance. By performing this preparation step in advance, the overall process complexity is managed while achieving the performance benefits of metal bitlines.
Solution Approach 2:
The patent utilizes parameter changes in the form of selective epitaxial growth conditions (temperature, pressure, gas composition) to control the base layer formation. By optimizing these parameters, the base layer achieves the desired properties for low-resistance metal deposition, allowing performance improvement while keeping process complexity可控 through parameter optimization rather than adding complex process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Metal BLs reduce resistance and improve performance in memory devices, enabling more efficient 3D memory structures with better space utilization and power consumption.
Implementation Method 1
Metal BLs reduce resistance and improve performance in memory devices
Data Source
AI summary
Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.