High-Density Metal Bonding Pads With Insulating Spacers
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Solution Overview
Problem
Existing methods for metal-to-metal bonding in semiconductor dies are complex and inefficient, requiring multiple steps and potentially leading to issues with bonding pad density and flatness.
Innovation Solution
A bonded assembly is formed using a first semiconductor die with first dielectric material layers, metal interconnect structures, a bonding-level dielectric layer embedding an electrically conductive bonding structure, and a dummy electrically conductive bonding structure. The assembly also includes insulating spacers laterally surrounding the bonding structures and vertically spaced from the second semiconductor die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-step methods are used to form bonding pads, then bonding pads can be created, but the process complexity increases and manufacturing efficiency decreases
Solution Approach 1:
The patent combines multiple bonding pad formation operations into a single integrated process. Conductive structures are formed that serve both as electrical interconnects and as bonding pads simultaneously, eliminating the need for separate bonding pad formation steps. This merging of functions reduces process complexity while maintaining bonding reliability.
Solution Approach 2:
The conductive structures embedded in the dielectric layer serve multiple functions: they act as electrical interconnects for signal transmission and as bonding pads for die attachment. This multi-functionality eliminates the need for dedicated bonding pad structures, simplifying the overall device architecture and manufacturing process.
2Quantity of substance
If bonding pad density is increased, then more connections can be made, but flatness between bonding pads and surrounding dielectric material deteriorates
Solution Approach 1:
The patent employs insulating spacer structures with varying heights and configurations around different bonding pads. These spacers are strategically placed to provide localized support and planarization, ensuring that each bonding pad maintains proper flatness regardless of its position or density in the array. This local quality approach allows high bonding pad density while preserving the required flatness for reliable bonding.
3Area of stationary object
If insulating spacers are positioned closer to bonding structures, then space is saved, but the risk of short circuits increases
Solution Approach 1:
The patent employs asymmetric insulating spacer configurations where spacers are positioned at specific locations around bonding structures rather than uniformly distributed. The spacer height and placement are optimized to provide maximum electrical isolation where needed while minimizing space consumption. This asymmetric arrangement achieves both compact die area utilization and reliable short circuit prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the bonding process, improves bonding pad density, and enhances the flatness between bonding pads and surrounding dielectric material, while reducing the likelihood of short circuits.
Implementation Method 1
performing an anisotropic etch process that etches materials of the insulating spacer material layer and the first-bonding-level dielectric layer to form a first-type insulating spacer
Data Source
AI summary
A bonded assembly includes a first semiconductor die bonded to a second semiconductor die. The first semiconductor die includes first dielectric material layers located on first semiconductor devices, first metal interconnect structures embedded in the first dielectric material layers and electrically connected to the first semiconductor devices, a first bonding-level dielectric layer located on the first dielectric material layers and embedding a first electrically conductive bonding structure that is electrically connected to one of the first metal interconnect structures, and further embedding a first dummy electrically conductive bonding structure having a lesser vertical extent than the first electrically conductive bonding structure and electrically isolated from the first metal interconnect structures, and a first-type insulating spacer embedded in the first bonding-level dielectric layer and laterally surrounding the first electrically conductive bonding structure and vertically spaced from the second semiconductor die and from the first dielectric material layers.