Metal Bump Test Circuit Layout to Prevent Probe Damage
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Solution Overview
Problem
Current electronic component manufacturing methods face challenges in performing electrical tests without damaging the components, particularly due to the need to test each re-distribution layer, which can lead to performance issues and reduced reliability.
Innovation Solution
The method involves creating an electronic component with an insulating layer and metal layers, where a first metal layer is disposed on the insulating layer, and a second metal layer is stacked on top, allowing for the use of part of the first metal layer as an auxiliary circuit for electrical testing to prevent damage during testing, thereby improving the component's performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical tests are performed on each re-distribution layer, then manufacturing quality control is improved, but the metal bumps may be damaged during testing
Solution Approach 1:
The patent segments the testing function by creating separate auxiliary circuit regions that are spatially distinct from the metal bump regions. The insulating layer is divided into first regions (for metal bumps) and second regions (for auxiliary circuits), allowing electrical testing to be performed on the auxiliary circuits without direct contact with or damage to the metal bumps.
Solution Approach 2:
The patent introduces auxiliary circuits as intermediary elements for electrical testing. These auxiliary circuits are electrically connected to the metal bumps through the insulating layer but provide an indirect testing path, allowing quality control measurements to be taken without applying test signals directly to the metal bumps themselves, thereby preventing damage.
2Adaptability or versatility
If the number of I/O is increased to satisfy functional requirements, then device functionality is improved, but circuit I/O design becomes more difficult
Solution Approach 1:
The patent transitions from a two-dimensional planar I/O arrangement to a three-dimensional vertical architecture. Metal bumps are stacked in multiple layers on the insulating substrate, allowing I/O expansion in the vertical dimension rather than requiring increased horizontal spacing. This enables higher I/O density without proportionally increasing design complexity.
Solution Approach 2:
The patent implements a nested structure where multiple metal bump layers are stacked vertically, with each layer containing multiple bumps. The auxiliary circuits are also nested within the insulating layer structure. This nested arrangement allows numerous I/O connections to be packed into a compact footprint, improving functionality without linearly increasing design complexity.
Data Source
AI summary
A manufacturing method of electronic components includes the steps of: providing an insulating layer including a first region and a second region; providing a first metal layer disposed in the first region of the insulating layer; providing a second metal layer disposed on the first metal layer; providing a metal line in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer; and removing the metal line to form an electronic component, wherein the electronic component includes the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer.