Metal-Capacitor eFlash Cell Array for High-Density Integration
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Solution Overview
Problem
Conventional logic-compatible flash memory designs face challenges in high-density integration due to the large size of transistors, particularly the coupling transistor, which increases macro area and manufacturing complexity as semiconductor processes shrink.
Innovation Solution
Implementing a non-volatile memory cell structure that uses metal capacitors instead of floating gates, reducing the size of transistors by incorporating parallel-plate metal capacitors to create capacitance and achieve equivalent coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating-gate transistors are used for logic-compatible flash memory, then non-volatile data storage is achieved, but transistor size increases and macro area expands
Solution Approach 1:
The patent merges the capacitor structure with the transistor gate region, forming a unified component where the capacitor plates are integrated into the gate structure. This merging eliminates the need for separate capacitor components and reduces the overall footprint, allowing non-volatile storage functionality without expanding macro area.
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional stacked architectures, placing capacitor plates in vertical layers above the transistor channel. This dimensional transition enables high-capacitance storage within a compact footprint, resolving the contradiction between storage capacity and macro area.
2Reliability
If coupling transistor width is increased to achieve dominant effect during programming, then programming reliability is improved, but device area increases
Solution Approach 1:
The patent changes the physical state and electrical characteristics of the gate structure by introducing capacitor plates with specific dielectric materials. This parameter change enables enhanced coupling effect without increasing transistor width, as the capacitor structure provides the necessary electrical dominance during programming operations.
Solution Approach 2:
The patent employs composite material structures combining conductive capacitor plates with dielectric layers in a stacked configuration. This composite approach creates a multi-functional gate structure that achieves both programming reliability and area efficiency by integrating capacitive coupling within the gate region itself.
3Quantity of substance
If semiconductor manufacturing processes shrink to smaller nodes, then integration density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the gate structure into distinct functional regions: transistor channel, capacitor plates, and dielectric layers. This segmentation allows independent optimization of each component and simplifies manufacturing by enabling standard fabrication processes to create the stacked capacitor-transistor architecture without requiring complex new processing steps.
Solution Approach 2:
The patent designs a universal gate structure that serves multiple functions: transistor gating, capacitive coupling, and charge storage. This multi-functionality reduces the number of separate components needed, thereby reducing manufacturing complexity while maintaining high integration density achievable at smaller semiconductor nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of metal capacitors allows for a significant reduction in transistor size, facilitating high-density integration of embedded non-volatile flash memory without increasing macro area, thus addressing the scalability issues of traditional designs.
Implementation Method 1
a main metal layer is configured with a plurality of metal plates that are spaced apart with one or more predefined intervals forming a parallel-plate structure in a lateral direction
Implementation Method 2
An electrical charge is applied to the floating gate to program (write) data, and a higher voltage is applied to erase data by removing the trapped electrons
Implementation Method 3
Data is written (programmed) using a process called hot-electron injection or Fowler-Nordheim tunneling. A high voltage is applied between the control gate and the source/drain. This forms a strong electric field that accelerates electrons from the channel region.
Implementation Method 4
Some of these high-energy electrons tunnel through the thin oxide layer and become trapped in the isolated floating gate.
Data Source
AI summary
A nonvolatile memory unit cell can comprises: a P-type substrate; a set of one or more P-type transistors with floating gates, each having an active drain and source region on an N-well doped on the P-type substrate; one N-type transistor sharing the floating gate of the one or more P-type transistors, with active drain and source regions doped on the P-type substrate; a polysilicon layer above the gate regions of the P-type and N-type transistors; a plurality of control lines to apply voltages to the gates, source, and drains of the transistors; and a plurality of metal layers above the polysilicon layer, wherein a main metal layer (1) is configured with a plurality of metal plates spaced apart with one or more intervals forming a parallel-plate structure in a lateral direction and (2) forms a parallel plate structure in a horizontal direction with at least one parallel metal layer.