Metal-Capped Fin Interconnects With Bottom-Up Plug Filling
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Solution Overview
Problem
Semiconductor devices with narrow dimensions face increased resistivity and void formation due to high aspect ratios of metal liners and barrier layers, which can lead to inefficient voltage transmission and manufacturing challenges.
Innovation Solution
The implementation of bottom-up metal-on-metal deposition techniques allows for the direct deposition of metal plugs on metal caps within recesses without the need for metal liners or barrier layers, reducing voids and maintaining low resistivity, thereby enabling smaller feature sizes and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal liners and barrier layers are used in narrow interconnect structures, then electrical connectivity is provided, but resistivity increases and voids form due to high aspect ratios
Solution Approach 1:
The patent removes metal liners and barrier layers from the interconnect structure, extracting the harmful elements that cause high resistivity and void formation. The metal cap is deposited directly on the conductive structure without intermediate layers, eliminating the source of the problem while maintaining electrical connectivity.
Solution Approach 2:
The patent employs a composite interconnect structure consisting of a metal cap made from a specific material composition (e.g., cobalt-based alloy with boron and carbon) that inherently provides both low resistivity and void-free filling capability, replacing the traditional multi-layer composite of conductor + liner + barrier.
2Reliability
If traditional multi-layer interconnect structures are used, then electrical connectivity is achieved, but manufacturing complexity and time increase due to multiple deposition steps
Solution Approach 1:
The patent extracts and removes the metal liner and barrier layer deposition steps from the manufacturing process, reducing the number of process steps from multiple sequential depositions to a single metal cap deposition, thereby simplifying the overall manufacturing complexity.
Solution Approach 2:
The patent merges the functions of electrical connectivity, diffusion barrier, and adhesion into a single metal cap layer, combining multiple functional requirements into one material and process step, which reduces both manufacturing time and process complexity.
3Area of stationary object
If feature sizes are reduced to improve device density, then space is conserved, but resistivity increases and voids form in high aspect ratio structures
Solution Approach 1:
The patent changes the material parameters of the interconnect structure by using a metal cap with specific compositional parameters (e.g., cobalt-rich alloy with boron and carbon additives) that enable low-resistivity filling and void prevention even in high aspect ratio, narrow dimension structures, allowing continued scaling.
Solution Approach 2:
The patent uses a specially formulated composite metal cap material that combines multiple elements to achieve properties of low resistivity, high fillability, and void prevention, enabling the structure to maintain performance at reduced feature sizes where traditional materials would fail.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively fills recesses with metal plugs, reducing resistance and voids, allowing for smaller dimensions while maintaining low resistivity and reducing manufacturing time and costs by eliminating the need for additional layers.
Implementation Method 1
bottom-up metal-on-metal deposition of a metal plug within a recess formed within a dielectric layer... performing a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap
Data Source
AI summary
In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.