Metal-Capped Gate Structure to Prevent Contact-Etch Shorts

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Solution Overview

Problem

As semiconductor devices scale down to advanced technology nodes, the complexity of IC processing increases, and the process window narrows, leading to challenges in protecting spacer layers and preventing gate height reduction during contact formation, which can result in electrical shorts between the gate and adjacent source/drain structures.

Innovation Solution

Incorporating a metal cap layer over the gate structure to protect it and the spacer layers during subsequent manufacturing processes, such as etching, thereby preventing gate height loss and electrical shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If device dimensions are reduced to scale down semiconductor devices, then higher integration density is achieved, but gate height reduction and spacer layer damage occur during contact formation

Engineering Contradiction:
Improvedevice areaVSAvoidgate height
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

A metal cap layer is deposited over the gate structure before contact formation to preemptively protect the gate from etching damage. This preliminary protective action prevents gate height reduction that would otherwise occur during subsequent contact etching processes, resolving the contradiction between device scaling and gate height maintenance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal cap layer serves as an intermediary protective element between the gate structure and the etching process. This intermediate layer absorbs the harmful etching effects, preventing direct damage to the gate and spacer layers, thereby enabling precise manufacturing at scaled dimensions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of moving object

If device dimensions are reduced to scale down semiconductor devices, then higher integration density is achieved, but electrical shorts between gate and source/drain structures occur

Engineering Contradiction:
Improvedevice areaVSAvoidelectrical isolation
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The metal cap layer is applied in advance to establish electrical isolation protection before contact formation begins. This preliminary protective measure prevents electrical shorts between the gate and adjacent source/drain structures that would otherwise occur during subsequent processing steps at scaled dimensions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal cap layer acts as an intermediary barrier that maintains electrical isolation between the gate and source/drain structures. This intermediate protective layer prevents harmful electrical interactions during contact formation, ensuring reliability in scaled devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If conventional processing without metal cap is used, then process simplicity is maintained, but gate height loss and spacer damage occur

Engineering Contradiction:
Improveprocess stepsVSAvoidgate height
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The metal cap layer is deposited as a preliminary step before contact formation to protect the gate structure. This additional preliminary step prevents gate height loss and spacer layer damage that would otherwise occur, accepting increased process complexity as necessary to achieve the desired manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250331223A1Semiconductor device with metal cap on gate
Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250331223A1 patent drawing
  • US20250331223A1 patent drawing
  • US20250331223A1 patent drawing

AI summary

A device includes a gate, first and second spacer structures, a conductive cap, a dielectric structure, an interlayer dielectric (ILD) layer, and a source/drain conductive structure. The gate is over a substrate. The first and second spacer structures extend along first and second sidewalls of the gate, respectively. The conductive cap is over the gate. A top surface of the conductive cap is at a first level, and a top surface of first spacer structure is at a second level different than the first level. The dielectric structure is over the gate and has a top surface higher than the top surface of the conductive cap. The ILD layer is disposed over a source/drain feature formed over the substrate. The source/drain conductive structure extends through the ILD layer to electrically couple to the source/drain feature.