Metal Capping Layer Layout for TSV CMP Damage Avoidance
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Solution Overview
Problem
Conventional semiconductor fabrication processes damage metal capping layers during the formation of through-substrate vias (TSVs), leading to reduced electromigration resistance and increased failure rates in integrated circuits due to excessive planarization processes.
Innovation Solution
Forming TSVs before the TSV insert metallization layer, thereby avoiding additional chemical-mechanical-polish (CMP) processes that can damage metal capping layers, and ensuring these layers remain intact with a consistent thickness, thus enhancing electromigration resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional CMP processes are performed to form TSVs after metal capping layers are formed, then TSV formation is achieved, but the metal capping layers are damaged and their thickness is reduced
Solution Approach 1:
The patent applies preliminary action by forming the TSV structure before forming the metal capping layers. Specifically, the method forms a TSV opening, fills it with conductive material, and performs planarization to create a flat surface before depositing the metal interconnect layer and subsequent metal capping layers. This sequence ensures that the metal capping layers are deposited on a planarized surface and are not damaged by subsequent CMP processes used to form TSVs, thereby preserving their thickness and electromigration resistance.
2Ease of manufacture
If conventional fabrication processes are used with multiple CMP steps, then TSV formation is achieved, but device failure rate increases due to damaged metal capping layers
Solution Approach 1:
The patent applies preliminary action by forming the TSV structure before forming the metal capping layers. Specifically, the method forms a TSV opening, fills it with conductive material, and performs planarization to create a flat surface before depositing the metal interconnect layer and subsequent metal capping layers. This sequence ensures that the metal capping layers are deposited on a planarized surface and are not damaged by subsequent CMP processes used to form TSVs, thereby preserving their thickness and electromigration resistance.
Data Source
AI summary
Semiconductor structures and fabrication methods are provided. In one example, a method includes forming a first dielectric layer on a semiconductor structure. The semiconductor structure includes a substrate and a multi-layer interconnect (MLI) structure on the substrate. The MLI structure includes multiple metallization layers. The first dielectric layer is formed on a topmost metallization layer. The method further includes forming a through-substrate-via (TSV) opening extending vertically through the first dielectric layer and the multiple metallization layers into the substrate, forming a TSV in the TSV opening, performing a first planarization process to planarize the TSV, forming multiple first metal vias and first metal lines in the first dielectric layer after the first planarization process, forming multiple first metal capping layers respectively on the multiple first metal lines, and performing a second planarization process to planarize the first metal capping layers.