Metal-Catalyzed Wet Etching for Vertical Through-Silicon Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wafer level packaging technologies using through-silicon vias face challenges in achieving non-porous, vertically walled structures suitable for electrical interconnects, particularly for submounts and interposers, due to limitations in etching length scales and porosity issues.
Innovation Solution
The method involves metal-catalyzed chemical etching using an aqueous solution with an oxidizing agent and acid to form through-silicon vias with vertical sidewalls, where a noble metal structure is used to preferentially etch silicon substrate contact regions, allowing for the creation of high aspect ratio, non-porous vias with reduced thermal resistance and expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form through-silicon vias, then through-vias can be formed, but the vias exhibit porosity and non-vertical sidewalls which are unsuitable for electrical interconnects
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using a metal-catalyzed wet etching method with specific etchant compositions and controlled etching conditions. This enables precise control over etch rate and sidewall morphology, achieving vertical sidewalls and eliminating porosity in the through-vias, thereby making them suitable for electrical interconnects
Solution Approach 2:
The patent replaces conventional mechanical or plasma etching methods with a chemical wet etching process that is catalyzed by metal particles. This substitution allows for better control over the etching front propagation, resulting in clean, vertical sidewalls without the porosity issues associated with traditional methods
2Temperature
If existing through-silicon via formation processes are used, then vias can be created, but thermal resistance and thermal expansion issues persist
Solution Approach 1:
The patent achieves improved thermal performance by controlling the via formation process to create non-porous structures with vertical sidewalls. This reduces void spaces that would otherwise act as thermal insulators, thereby lowering thermal resistance. The precise control over via geometry also helps manage thermal expansion characteristics
3Ease of manufacture
If conventional etching is used, then through-vias can be formed, but the process is not cost-effective for production
Solution Approach 1:
The patent uses a disposable layer of metal particles (such as aluminum or other sacrificial metals) that are deposited on the silicon substrate to catalyze the wet etching process. These particles are consumed during etching and can be removed afterward, providing a low-cost method to achieve high-precision vertical via formation without requiring expensive equipment or complex process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the cost-effective production of silicon interposers with minimal porosity and improved thermal performance, facilitating the formation of electrically useful through-vias suitable for various applications, including photovoltaic modules.
Implementation Method 1
metal-catalyzed chemical etching to form structures in silicon that extend from a top surface of the substrate to the bottom surface of the substrate
Implementation Method 2
The etchant preferentially etches the silicon substrate contact regions compared to silicon substrate non-contact regions
Implementation Method 3
the etchant is an aqueous solution that comprises an oxidizing agent and an acid
Implementation Method 4
the force due to gravity acts on the noble metal structure in a direction from the silicon top support surface toward the bottom surface
Data Source
AI summary
Provided are methods for making a through-silicon via feature in a silicon substrate and related systems, such as by forming a noble metal structure on a silicon substrate support surface to generate silicon substrate contact regions that are in contact with or proximate to the noble metal structure; exposing at least a portion of the silicon substrate support surface and noble metal structure to an etchant to preferentially etch the silicon substrate contact regions compared to silicon substrate non-contact regions until the etch front reaches the silicon substrate bottom surface.