Metal Chalcogenide Interconnect Caps for Lower RC Delay
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Solution Overview
Problem
The increasing density of interconnects in integrated circuits leads to higher resistance-capacitance (RC) delay, which is not adequately addressed by conventional interconnect architectures.
Innovation Solution
Integrating a chalcogenation process to convert the top portion of interconnect line bulk materials into a metal chalcogenide cap, which reduces scattering resistance and maintains a negligible interconnect line volume penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect density is increased to meet transistor density requirements, then transistor integration is improved, but RC delay increases
Solution Approach 1:
The patent applies local quality by creating a cap structure with different material properties than the bulk interconnect material. The cap portion has reduced scattering resistance compared to the bulk material, providing localized improvement in electrical properties where it is most needed (at the surface/interface regions) while maintaining the overall interconnect density architecture.
2Ease of manufacture
If conventional interconnect architectures are used, then manufacturing simplicity is maintained, but scattering resistance is not adequately reduced
Solution Approach 1:
The patent employs composite materials by combining the bulk interconnect material with a cap material that has different properties (metal chalcogenide or crystalline structure). This composite structure provides reduced scattering resistance at the surfaces and interfaces while maintaining compatibility with conventional manufacturing processes like electroplating and annealing.
3Volume of moving object
If interconnect line volume is reduced to maintain density, then integration is improved, but resistance reduction benefit is limited
Solution Approach 1:
The patent applies parameter changes by modifying the crystalline structure and chemical composition of the interconnect material through controlled annealing and chalcogenation processes. These parameter changes transform the bulk material and cap material into metal chalcogenides with fundamentally different electrical properties, achieving resistance reduction without requiring volume reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The metal chalcogenide cap significantly reduces interconnect line resistance, leading to lower RC delay, improved performance, and reduced power consumption in integrated circuits.
Implementation Method 1
Integrating a chalcogenation process to convert the top portion of interconnect line bulk materials into a metal chalcogenide cap
Data Source
AI summary
Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.