Metal Chalcogenide Interconnect Liner for Lower RC Delay

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Solution Overview

Problem

The increasing density of interconnects in integrated circuits leads to higher resistance-capacitance (RC) delay, which is not effectively addressed by conventional interconnect architectures and liner materials, particularly in high-density transistor architectures.

Innovation Solution

The implementation of a two-dimensional (2D) metal chalcogenide liner on the sidewalls of interconnect structures, formed through chalcogenation of a backbone material, which reduces electrical resistance and scattering, and is compatible with cryogenic operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interconnect density is increased to meet transistor density requirements, then IC performance is improved, but RC delay increases

Engineering Contradiction:

ImproveIC performanceVSAvoidRC delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent changes the material parameters of the liner from conventional materials (tantalum, tungsten) to metal chalcogenide materials (MoS2, WS2, MoSe2, WSe2). These materials have fundamentally different electrical properties with lower resistivity, directly addressing the RC delay issue while maintaining the required interconnect density for high-performance ICs

Inventive Principle:

Principle #35Parameter changes

2Reliability

If conventional liner materials are used to prevent diffusion and improve adhesion, then reliability is improved, but electrical resistance increases

Engineering Contradiction:

Improvediffusion barrier and adhesionVSAvoidelectrical resistance

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent employs metal chalcogenide materials that combine multiple functions in a single liner layer. These materials simultaneously provide diffusion barrier properties, adhesion enhancement, and low electrical resistance, eliminating the need for separate functional layers and reducing overall interconnect resistance while maintaining reliability

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The patent transitions from conventional metal liners with high resistivity to metal chalcogenide liners with inherently lower resistivity. The chalcogenide materials exhibit superior electrical conductivity while maintaining the protective and adhesive functions, directly resolving the contradiction between reliability and electrical resistance

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The 2D metal chalcogenide liner significantly reduces electrical resistance and enhances IC performance, particularly at cryogenic temperatures, by minimizing interconnect resistance and maintaining conductivity.

Implementation Method 1

The liner material is a two-dimensional (2D) metal chalcogenide that can reduce scattering and electrical resistance of interconnect metallization features

Methodology Applied

Scientific EffectElectron scattering:

Data Source

PatentUS12512365B2Integrated circuit interconnect structures with a metal chalcogenide liner

Publication Date: 2025.12.30 INTEL CORP

AI summary

Integrated circuit interconnect structures including an interconnect metallization feature comprising a sidewall reacted with a chalcogen into a low resistance liner. A portion of a backbone material or a metal seed layer may be advantageously converted into a metal chalcogenide, which can lower scattering resistance of an interconnect feature relative to alternative diffusion barrier materials, such a tantalum. Scattering resistance of such metal chalcogenide liner materials may be further reduced by actively cooling an IC, for example to cryogenic temperatures.