Metal-Compound Conductive Pillars for Low-Resistance Chip Interconnects
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Solution Overview
Problem
The miniaturization of chips in electronic devices poses challenges in interconnection and coupling between conductive patterns, as the reduction in conductive pattern size increases difficulty in interconnection and coupling, and the characteristics of conductive pillars, such as resistance and preparation process, directly affect the interconnection and coupling effect and chip yield rate.
Innovation Solution
A chip structure is proposed that includes a first conductive pillar with a metal pillar and a metal compound layer, where the metal compound layer is between the metal pillar and the dielectric layer, covering at least a part of the metal pillar's side surface, and the first conductive pillar is in contact with the dielectric layer through the metal compound layer and the uncovered side surface of the metal pillar, without a barrier layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of the conductive pattern is reduced to meet miniaturization requirements, then the chip size is reduced, but the interconnection and coupling difficulty between conductive patterns increases
Solution Approach 1:
The patent changes the material composition and structural parameters of the conductive pillar by introducing a metal compound layer (such as oxide, nitride, or carbide layer) with specific physical and chemical properties. This layer has different conductivity, adhesion, and chemical resistance characteristics compared to the base metal, enabling optimized interconnection performance in miniaturized structures.
Solution Approach 2:
The conductive pillar is constructed as a composite structure comprising a metal core and a metal compound layer. This composite design combines the high conductivity of the metal core with the superior adhesion and chemical stability of the metal compound layer, achieving both electrical performance and structural reliability in miniaturized chips.
2Reliability
If a barrier layer is added between the conductive pillar and dielectric layer to prevent solution penetration, then chip reliability is improved, but the resistance of the conductive pillar increases and manufacturing complexity increases
Solution Approach 1:
The metal compound layer serves as an intermediary between the metal conductive pillar and the dielectric layer. It provides chemical barrier functionality to prevent solution penetration while maintaining electrical conductivity, eliminating the need for separate barrier layers and reducing overall resistance.
Solution Approach 2:
The patent controls the thickness and composition parameters of the metal compound layer to optimize its dual functionality. By adjusting parameters such as layer thickness (typically 1-10 nm) and chemical composition (oxide, nitride, carbide ratios), the layer achieves sufficient chemical barrier properties while minimizing resistance increase.
3Manufacturing precision
If the depth-to-width ratio of the conductive pillar is increased to reduce resistance, then the interconnection effect is improved, but the gap defect between the conductive pillar and dielectric layer becomes more prominent
Solution Approach 1:
The metal compound layer acts as an intermediary that fills and seals the gap defects between the high aspect-ratio conductive pillar and the dielectric layer. This prevents solution penetration into the gaps while maintaining the low-resistance design with high depth-to-width ratio.
Solution Approach 2:
The metal compound layer is selectively formed at the interface region between the conductive pillar and dielectric layer, providing localized gap-filling and sealing functionality. The layer's properties are optimized specifically for this interface region, with higher density and better adhesion characteristics at the boundaries.
Data Source
AI summary
A integrated circuit (IC) chip includes a dielectric layer and a first conductive pillar disposed in the dielectric layer. The first conductive pillar runs through the dielectric layer in a thickness direction of the dielectric layer. The chip further includes a first conductive pattern and a second conductive pattern that are located on two opposite sides of the first conductive pillar and are coupled to the first conductive pillar. The first conductive pillar includes a metal pillar and a metal compound layer. The metal compound layer is located between the metal pillar and the dielectric layer and covers a part of a side surface of the metal pillar. The first conductive pillar is directly in contact with the dielectric layer, and no barrier layer is disposed between the first conductive pillar and the dielectric layer.