Metal Contact Isolation Layout for Self-Aligned FinFET Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of forming isolation features between source/drain metal contacts becomes more difficult as device sizes decrease, leading to issues such as hard mask peel-off during patterning and reduced device time-dependent dielectric breakdown (TDDB) performance.
Innovation Solution
The formation of contact isolations is achieved by stacking them between adjacent gate structures in a self-aligned manner along the fin lengthwise direction, separating adjacent source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes continue to decrease, then production efficiency increases and costs decrease, but forming isolation features between source/drain metal contacts becomes more challenging
Solution Approach 1:
The patent performs preliminary actions by forming mandrel structures and applying first hard masks before the actual isolation feature formation. The mandrel structures are prepared in advance with specific geometries that guide subsequent self-aligned etching processes, ensuring isolation features are correctly positioned before metal contact patterning occurs.
Solution Approach 2:
The patent introduces intermediary structures including mandrels, spacers, and multiple hard mask layers that mediate between the lithography pattern and the final isolation features. These intermediary elements enable precise positioning of isolation features without requiring direct lithographic patterning at the smallest dimensions.
2Quantity of substance
If spacing between source/drain metal contacts is reduced, then device density increases, but hard mask peel-off occurs during patterning
Solution Approach 1:
The patent employs composite material structures with multiple hard mask layers having different material compositions and properties. The first hard mask layer is formed with specific materials that provide adhesion to the mandrel structure, while subsequent layers provide pattern definition. This composite approach prevents peel-off by ensuring strong interfacial adhesion at each layer.
Solution Approach 2:
The patent applies different material properties and thicknesses at different locations and interfaces. The hard mask layers have varying compositions optimized for specific functions: adhesion at the mandrel interface, pattern fidelity at the lithography interface, and etch selectivity at the etching interface. This local optimization prevents peel-off while maintaining pattern integrity.
3Quantity of substance
If spacing between source/drain metal contacts is reduced, then device density increases, but time dependent dielectric breakdown performance decreases
Solution Approach 1:
The self-aligned isolation formation process inherently provides adequate spacing and isolation between adjacent metal contacts without requiring additional design margins. The isolation features automatically position themselves to provide sufficient dielectric separation, ensuring TDDB performance is maintained even as device density increases.
Data Source
AI summary
A method includes forming a fin protruding from a substrate, forming first and second dummy gates across the fin, depositing first and second gate spacers on sidewalls of the first and second dummy gates, respectively, forming a source/drain epitaxial feature over the fin and between the first and second dummy gates, depositing an interlayer dielectric layer over the source/drain epitaxial feature and between the first and second gate spacers, replacing the first and second dummy gates with first and second metal gates, respectively, patterning the interlayer dielectric layer to form an opening between the first and second gate spacers, forming a dielectric cut feature in the opening, after the forming of the dielectric cut feature, etching the interlayer dielectric layer to form a trench between the first and second metal gates, and forming a source/drain contact in the trench and in electrical coupling with the source/drain epitaxial feature.