Metal Contact Hole Layout for Overlay-Tolerant Semiconductor Interconnects
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Solution Overview
Problem
Current photolithographic technologies face challenges with unsatisfactory layer-to-layer overlay alignments, leading to poor photoresist patterns that require additional etch operations to compensate, increasing rework rates and potentially affecting the electrical resistance between metal layers.
Innovation Solution
A method is introduced to form additional recesses in the interlayer dielectric (ILD) layer proximal to lower metal layers, which are then filled with metals to create upper metal layers that contact the sidewalls of the lower layers, enhancing the contacting area and reducing electrical resistance, even when the photoresist pattern is not well-aligned.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional etch operations are performed to compensate for unsatisfactory overlay alignment, then the photoresist pattern alignment is improved, but the manufacturing complexity and rework rate increase
Solution Approach 1:
The patent transitions from a single-layer metal structure to a multi-layer metal structure with vertical stacking. By adding upper metal layers over lower metal layers with increased contacting area, the solution addresses alignment issues in the horizontal plane by utilizing the vertical dimension, thereby compensating for overlay alignment errors without requiring additional etch operations.
Solution Approach 2:
The patent forms upper metal layers in advance that are designed to contact the sidewalls of lower metal layers. This preliminary structuring ensures that even if photoresist alignment is poor, the pre-formed geometry provides adequate electrical contact, eliminating the need for compensatory etch operations.
2Manufacturing precision
If the photoresist pattern is not well-aligned with the lower metal layer, then the overlay specification is violated, but the electrical resistance between metal layers may increase
Solution Approach 1:
The patent changes the geometric parameters of the metal structure by creating upper metal layers with larger contacting area with respect to lower metal layers. This parameter change ensures that even when horizontal alignment is poor, the increased vertical contact area maintains low electrical resistance, thereby decoupling alignment precision from electrical performance.
Solution Approach 2:
The patent utilizes the vertical dimension by forming upper metal layers that extend downward to contact the sidewalls of lower metal layers. This three-dimensional configuration compensates for two-dimensional alignment errors, ensuring reliable electrical connection even when photoresist patterns are misaligned.
3Reliability
If additional metal layers are formed to increase contacting area, then the electrical resistance is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent merges multiple metal layers into a unified conductive structure where upper metal layers are directly connected to lower metal layers through sidewall contact. This merging creates an integrated multi-layer system that achieves low electrical resistance while managing structural complexity through functional integration rather than separate components.
Solution Approach 2:
The patent utilizes the curved sidewall surface of lower metal layers as a contact interface for upper metal layers. By forming contacts along the curved sidewall rather than only at flat surfaces, the design increases contacting area and improves electrical connection while maintaining a relatively simple layered structure.
Data Source
AI summary
The present disclosure provides a method for manufacturing a semiconductor device. The method includes: forming a first metal structure in a first ILD layer; planarizing the first metal structure and the first ILD layer, wherein the planarizing generates a groove at an interface of the first metal structure and the first ILD layer; forming an ESL on the first metal structure and the first ILD layer; forming a second ILD layer on the ESL; performing a first etch to remove a portion of the second ILD layer to form a first opening; performing a second etch to remove a portion of the ESL through the opening; performing a third etch to remove a portion of the first ILD layer through the first opening to form a second opening in the first ILD layer; and enlarging the second opening to connected with the groove to form a contact hole.