Semiconductor Metal-Containing Layer Selective Deposition

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Solution Overview

Problem

Existing FinFET manufacturing processes are inadequate for continued device scaling-down, requiring improvements in circuit integration and manufacturing efficiency.

Innovation Solution

The process involves forming a mask structure over a gate structure and selectively depositing a metal-containing layer over a contact without additional patterning and polishing, using high etching selectivity materials like silicon oxide or silicon nitride to simplify manufacturing and reduce the risk of electrical shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If additional patterning and polishing processes are used to deposit metal-containing layer, then manufacturing precision is improved, but device complexity and manufacturing time increase

Engineering Contradiction:
Improvemetal-containing layer deposition precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The metal-containing layer is selectively deposited on the contact structure through self-aligned deposition processes, where the layer automatically forms only on exposed metal surfaces without requiring additional patterning steps. This self-service mechanism eliminates the need for separate photolithography and etching processes while maintaining precise layer placement.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The contact structure is prepared in advance with specific surface properties and geometry that enable selective metal-containing layer deposition. The preliminary formation of the contact structure through prior processing steps creates the conditions necessary for subsequent selective deposition without additional patterning.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If conventional FinFET manufacturing processes are used, then manufacturing simplicity is maintained, but device scaling-down capability is insufficient

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoiddevice scaling precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The manufacturing process utilizes parameter changes in the deposition conditions, such as temperature, pressure, and precursor flow rates, to achieve selective metal-containing layer formation. These parameter adjustments enable precise control over layer deposition without requiring complex additional processing steps, thus supporting device scaling while maintaining manufacturing simplicity.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If metal-containing layer is deposited without selective formation, then manufacturing time is reduced, but electrical short risk increases

Engineering Contradiction:
Improvemanufacturing throughputVSAvoidelectrical short prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The metal-containing layer acts as an intermediary protective layer between the contact structure and subsequent processing steps. This layer selectively covers the contact structure while leaving other areas exposed, preventing electrical shorts during subsequent manufacturing operations without requiring additional protective measures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process, reduces material loss during etching, and effectively protects metal gate structures, enhancing the integration and performance of semiconductor devices.

Implementation Method 1

selectively depositing a metal-containing layer over a contact without additional patterning and polishing

Methodology Applied
Scientific EffectSelective deposition: Deposition (physical)

Data Source

PatentUS11201232B2Semiconductor structure with metal containing layer
Publication Date: 2021.12.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11201232B2 patent drawing
  • US11201232B2 patent drawing
  • US11201232B2 patent drawing

AI summary

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a source/drain structure formed adjacent to the gate structure in the substrate and a contact formed over the source/drain structure. The semiconductor structure further includes a metal-containing layer formed over the contact and a dielectric layer covering the gate structure and the metal-containing layer. The semiconductor structure further includes a first conductive structure formed through dielectric layer and the metal-containing layer and landing on the contact. In addition, a bottom surface of the metal-containing layer is higher than a top surface of the gate structure.