Metal Control Gate Capacitive Coupling for Low Voltage Programming
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Solution Overview
Problem
Conventional semiconductor storage devices with polysilicon control and floating gates require high programming voltages, limiting their suitability for deep sub-micron technologies due to design rules and alignment challenges, and are costly to manufacture.
Innovation Solution
A semiconductor storage device with a metal control gate structure adjacent to a polysilicon floating gate, capacitively coupled to enhance capacitive coupling and reduce programming voltage requirements, utilizing design rules that allow closer metal-to-polysilicon spacings and larger metal structures for increased capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon control gate is placed on top of the polysilicon floating gate, then the storage device can be programmed, but a relatively high voltage is required for programming which makes such arrangements unsuitable for deep sub-micron technologies
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the control gate and floating gate to create a capacitor structure. This intermediary enables capacitive coupling that allows programming at lower voltages suitable for deep sub-micron technologies, resolving the contradiction between programming capability and programming voltage requirements
Solution Approach 2:
The patent changes the material parameter of the control gate from polysilicon to metal, and introduces a dielectric layer with specific permittivity properties. These parameter changes enable the control gate to exert stronger electric field influence on the floating gate at lower voltages, solving the high voltage programming issue while maintaining programming capability
2Use of energy by moving object
If a polysilicon control gate is placed adjacent to a polysilicon floating gate with capacitive coupling, then lower programming voltages are achieved, but design rules impose a lower limit on device size and require separation of multiple poly-Si layers by special dielectrics
Solution Approach 1:
The patent changes the control gate material from polysilicon to metal, which eliminates the need for special dielectric separation between poly-Si layers. This parameter change simplifies the device structure and manufacturing process while maintaining the capacitive coupling mechanism that enables lower programming voltages
Solution Approach 2:
The patent merges the control gate and floating gate into a single capacitive coupling structure with a dielectric layer, eliminating the need for separate poly-Si layer processing and alignment. This merging reduces device complexity and manufacturing steps while achieving the desired low-voltage programming capability
3Reliability
If polysilicon structures are separated by special dielectrics with careful alignment, then capacitive coupling is achieved, but the cost of the device increases
Solution Approach 1:
The patent changes the control gate material from polysilicon to metal, which simplifies the manufacturing process by eliminating the need for special dielectric separation and careful alignment of multiple poly-Si layers. This parameter change reduces manufacturing complexity and cost while maintaining effective capacitive coupling between the control gate and floating gate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The metal control gate structure significantly increases capacitive coupling, reducing the minimum voltage needed for programming and erasing, improving the device's applicability in deep sub-micron technologies while minimizing poly depletion issues and enhancing read-out speed.
Implementation Method 1
a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to the floating gate
Data Source
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AI summary
The application discloses a semiconductor storage device (100, 200, 300) comprising a semiconductor substrate (112) having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate (122) placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material (124); and a metal control gate structure (126, 226, 326) adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. The application further discloses a method of manufacturing such a semiconductor storage device (100, 200, 300).