Metal-Core PCB Layout for Ultra-Narrow High-Current Pulses
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Solution Overview
Problem
Current metal-core printed circuit boards (PCBs) face limitations in generating ultra-narrow, high-current pulses due to parasitic inductance, which increases the size and cost of PCBs, and reduces structural integrity, making it challenging to achieve peak currents greater than 50A with a full-wave half-maximum pulse width of less than 10 ns.
Innovation Solution
A metal-core printed circuit board (MCPCB) design featuring a rigid metal heat sink layer with a dielectric layer thickness of less than 0.007 inches, eliminating additional heat sinking components and using polymer dielectric materials with a lower dielectric constant than FR-4, positioned between conductive layers to reduce parasitic inductance while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the dielectric thickness is reduced to decrease parasitic inductance, then the current ramp rate increases, but the structural integrity and reliability of the PCB deteriorates
Solution Approach 1:
The patent employs a composite PCB structure consisting of multiple layers including conductive traces, dielectric layers, and a metal core layer. This composite construction allows the thin dielectric layer (less than 0.007 inches) to provide electrical isolation while the metal core and outer substrate layers provide mechanical strength and structural support, resolving the contradiction between reduced inductance and maintained integrity
Solution Approach 2:
The patent applies different material properties to different regions of the PCB. The dielectric layer is localized to specific regions where electrical isolation is needed, while the metal core and substrate provide structural support in areas where mechanical strength is required. This localized application of different material qualities allows simultaneous optimization of both electrical performance and structural integrity
2Speed
If multiple circuit elements are used in parallel to reduce circuit inductance, then the current ramp rate increases, but the PCB assembly size and cost increase
Solution Approach 1:
The patent changes the fundamental parameter of dielectric thickness to achieve reduced inductance. By reducing the dielectric thickness between conductive layers, the parasitic inductance is decreased without requiring multiple parallel circuit elements. This parameter change achieves the desired current ramp rate improvement while maintaining a compact PCB assembly size
3Power
If the dielectric thickness is reduced to decrease parasitic inductance, then the peak current increases, but the manufacturing complexity and cost increase
Solution Approach 1:
The multi-layer composite structure with standardized thin dielectric layers between conductive planes provides a manufacturable solution. The composite construction allows the use of established PCB fabrication techniques while achieving the reduced inductance necessary for high peak current capability
4Speed
If broad traces and minimized dielectric thickness are used to reduce PCB inductance, then the current ramp rate increases, but the PCB size and cost increase
Solution Approach 1:
The patent transitions from planar trace configurations to a three-dimensional multi-layer structure. By stacking conductive layers separated by thin dielectric layers, the patent achieves reduced inductance through vertical arrangement rather than requiring larger horizontal trace dimensions. This dimensional change allows compact PCB size while maintaining high current ramp rate performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MCPCB achieves peak currents greater than 50A with a full-wave half-maximum pulse width of less than 10 ns, outperforming conventional PCBs in terms of current capacity and size without increasing costs or compromising structural integrity.
Implementation Method 1
At least one electrically insulating dielectric layer is positioned between the conductive top layer and rigid, metal heat sink layer, wherein the dielectric layer has a thickness of less than 0.007 inches
Implementation Method 2
a rigid, metal heat sink layer
Data Source
AI summary
A metal-core printed circuit board (MCPCB) and method of generating an ultra-narrow, high-current pulse driver with a MCPCB is provided. The MCPCB includes a rigid, metal heat sink layer and at least one electrically conductive top layer. At least one electrically insulating dielectric layer is positioned between the conductive top layer and rigid, metal heat sink layer, wherein the dielectric layer has a thickness of less than 0.007 inches.