Metal Die Attach Layer for Multichip Semiconductor Packages
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Solution Overview
Problem
Conventional die attach solutions using metal particle-filled polymers exhibit significant thermal and electrical resistance, which is inadequate for modern compact and high-integration electronic systems, and solder die attach, while offering better thermal and electrical conductivity, is expensive and limited to solderable surfaces, causing temperature-induced stresses during the reflow process.
Innovation Solution
A leadless packaged multichip semiconductor device with a metal substrate featuring a through-hole aperture and a plated metal die attach layer between the bottom semiconductor die's back side metal layer and the substrate, utilizing electroplating to form a conductive layer that reduces thermal and electrical resistance while avoiding temperature-induced stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal particle filled polymer die attach is used, then ease of manufacture is improved, but thermal conductivity and electrical conductivity deteriorate
Solution Approach 1:
The patent changes the fundamental parameter of die attach material from polymer-based to pure metal, transforming the thermal and electrical conductivity properties while maintaining manufacturing simplicity through direct metallurgical bonding processes
Solution Approach 2:
The patent employs composite metal structures including copper and copper alloy layers combined with bonding pads, creating a multi-layer composite die attach system that optimizes both thermal management and electrical connectivity while preserving ease of manufacture
2Reliability
If solder die attach is used, then thermal conductivity and electrical conductivity are improved, but cost increases and adaptability deteriorates
Solution Approach 1:
The patent creates a universal die attach solution using copper and copper alloy layers that can be applied to various semiconductor substrates regardless of solderability, enabling the same metallurgical bonding process to work across different material platforms and device types
Solution Approach 2:
The patent replaces expensive solder materials with cost-effective copper and copper alloy die attach layers, reducing material cost while maintaining superior thermal and electrical conductivity performance through direct metallurgical bonding
3Reliability
If solder die attach with reflow process is used, then thermal conductivity and electrical conductivity are improved, but stress on semiconductor die increases
Solution Approach 1:
The patent changes the processing temperature parameter from high-temperature solder reflow to lower-temperature metallurgical bonding, reducing thermal stress on semiconductor die while achieving equivalent or superior electrical conductivity through direct metal-to-metal bonding
Solution Approach 2:
The patent converts the potential harm of high-temperature processing into benefit by using controlled metallurgical bonding at optimized temperatures that create strong atomic-level bonds between copper layers, achieving both low stress and high conductivity simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a high thermal conductivity die attach with low electrical resistance, suitable for compact electronic systems, without the expense and limitations of solder die attach, and minimizes stress on semiconductor dies during the attachment process.
Implementation Method 1
The solution provides a high thermal conductivity die attach with low electrical resistance
Implementation Method 2
utilizing electroplating to form a conductive layer that reduces thermal and electrical resistance
Implementation Method 3
utilizing electroplating to form a conductive layer
Data Source
AI summary
A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.