Metal-Enhanced Select Gate for Flash Memory Leakage Reduction
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Solution Overview
Problem
As flash memory cells shrink in size, the thinning of silicon dioxide as a gate dielectric leads to increased oxide leakage current, compromising the select gate's current drive and overall performance.
Innovation Solution
The implementation of a metal-enhanced gate structure using high-K dielectric materials such as HfO2, ZrO2, or TiO2, combined with a work function metal layer and silicide, to enhance the select gate's performance by reducing leakage current and increasing current drive.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If silicon dioxide thickness is reduced to increase gate capacitance, then current drive is improved, but oxide leakage current increases significantly
Solution Approach 1:
The patent applies composite materials by combining high-K dielectric materials (such as HfO2, ZrO2, or TiO2) with metal layers (titanium nitride, tungsten, or tungsten silicide) to form a composite gate structure. This composite approach allows achieving high gate capacitance without the leakage problems of thin silicon dioxide, as the high-K dielectric provides superior electrical insulation while the metal layers tune the work function for optimal device performance.
Solution Approach 2:
The patent changes the dielectric constant parameter by replacing silicon dioxide (K≈3.9) with high-K dielectric materials (K>10). This parameter change enables maintaining adequate gate capacitance with thicker effective dielectric layers, thereby preventing leakage current while preserving current drive capability. The work function of the gate is also adjusted by selecting appropriate metal materials.
2Area of moving object
If memory cell size is reduced, then device density is improved, but gate dielectric performance deteriorates
Solution Approach 1:
As memory cells shrink, the patent employs composite high-K dielectric and metal gate structures to maintain reliable gate dielectric performance. The high-K dielectric layer provides robust electrical insulation even in scaled devices, while the metal gate materials allow precise work function tuning to optimize threshold voltage and prevent leakage, ensuring reliable operation in miniaturized memory cells.
Solution Approach 2:
The patent addresses reliability in scaled devices by changing the dielectric constant parameter to high-K materials, which maintain adequate capacitance and insulation properties even when device dimensions are reduced. This parameter change prevents the deterioration of gate dielectric performance that would otherwise occur with conventional silicon dioxide in nanoscale devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces oxide leakage current and enhances the speed and performance of the memory cell by improving the select gate's current drive, addressing the limitations of conventional silicon dioxide gate dielectrics.
Implementation Method 1
a high K dielectric layer... positioned over and insulated from the channel region
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
A non- volatile memory cell including a substrate having first and second regions with a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over and insulated from a second portion of the channel region which is adjacent to the second region. The select gate includes a block of polysilicon material and a work function metal material layer extending along bottom and side surfaces of the polysilicon material block. The select gate is insulated from the second portion of the channel region by a silicon dioxide layer and a high K insulating material layer. A control gate is disposed over and insulated from the floating gate, and an erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.