Metal Etch-Stop Interconnect Patterning Against Fluorine Damage
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Solution Overview
Problem
Existing methods for forming interconnect structures in integrated circuits (ICs) using advanced materials can inadvertently damage underlying dielectric and conductive features due to the use of fluorine-containing gases during etching processes.
Innovation Solution
Implementing a conductive etch-stop layer and a metal-based hard mask layer with specific compositions to provide etching selectivity, allowing for the direct patterning of conductive lines while minimizing damage to dielectric layers, and using a wet etching process to remove the hard mask layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fluorine-containing gases are used for etching conductive lines, then etching efficiency is improved, but underlying dielectric features and nearby conductive features are inadvertently damaged
Solution Approach 1:
A metal-based etch-stop layer is introduced as an intermediary between the conductive lines and the dielectric features. This layer selectively stops the fluorine-containing etchant, protecting the underlying dielectric and nearby conductive features from damage while allowing efficient etching of the conductive lines above it.
Solution Approach 2:
The etching process is segmented into multiple selective steps: first etching the conductive lines through the hard mask, then removing the hard mask, and finally removing the etch-stop layer. This segmentation allows control over etching depth and protects different layers at different stages.
2Manufacturing precision
If a hard mask layer is used for patterning conductive lines, then patterning precision is improved, but removal of the hard mask layer causes damage to underlying features
Solution Approach 1:
The metal-based etch-stop layer serves as a protective intermediary during hard mask removal. It allows selective removal of the hard mask using fluorine-containing gases while the etch-stop layer prevents damage to underlying dielectric and conductive features, and can be removed later using a different etching chemistry.
3Device complexity
If direct patterning of conductive lines is performed, then process complexity is reduced, but selectivity during etching becomes difficult to control
Solution Approach 1:
The metal-based etch-stop layer provides a selective barrier that enables direct patterning of conductive lines with controlled selectivity. It allows the fluorine-containing etchant to efficiently remove the conductive material while stopping at the etch-stop layer, achieving both process simplicity and etching selectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces unintended damage to dielectric features and improves the integrity of interconnect structures by ensuring selective etching and protecting conductive lines from damage during the patterning process.
Implementation Method 1
etching the second metal layer to form a conductive line
Implementation Method 2
gases generally employed for removing a dielectric hard mask layer after forming conductive lines
Implementation Method 3
using a wet etching process to remove the hard mask layer
Data Source
AI summary
A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.