Metal Fill Pattern Density for Through Die Via CMP
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Solution Overview
Problem
In die-stacking applications, the low metal pattern density around through die vias (TDVs) results in inefficient chemical metal polishing and variations in interconnect height, affecting the port depth of focus during optical lithography, leading to manufacturing yield issues.
Innovation Solution
A method and apparatus for designing integrated circuits (ICs) that involve analyzing layout data to identify TDV areas and creating a metal fill pattern with maximum metal width and minimum spacing to maximize metal fill density, eliminating design rule violations by defining holes in the metal fill pattern, and merging this pattern with the layout data to generate manufacturing masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated TDV regions are created with no metal or active layers within a predefined distance of TDVs, then TDV functionality is ensured, but metal pattern density around TDVs becomes low
Solution Approach 1:
The patent applies local quality by creating metal fill patterns specifically within TDV regions while maintaining the required clearance distances. Different regions of the IC have different metal densities: TDV regions have high metal density for CMP efficiency, while other regions maintain their original design. This localized approach ensures TDV functionality while improving overall metal pattern density.
Solution Approach 2:
The patent performs preliminary action by automatically generating metal fill patterns during the IC design phase before manufacturing. The system identifies TDV regions from layout data and pre-fills them with metal patterns that comply with design rules, ensuring that the metal density issue is resolved before the IC is fabricated, preventing yield problems in advance.
2Reliability
If low metal pattern density exists around TDVs, then TDV clearance is maintained, but chemical metal polishing efficiency decreases
Solution Approach 1:
The patent changes the metal density parameter within TDV regions by introducing metal fill patterns. The system calculates optimal metal fill densities and patterns that maintain the required clearance distances from TDV centers while providing sufficient metal presence for effective chemical mechanical polishing, thus improving polishing efficiency without compromising TDV clearance.
3Ease of manufacture
If low metal pattern density exists around TDVs, then design rules are satisfied, but interconnect height variation increases
Solution Approach 1:
The patent applies local quality by implementing metal fill patterns specifically in TDV regions to improve interconnect height uniformity. The metal fill density is locally increased in these regions while maintaining design rule compliance through enforced clearance distances, thereby reducing CMP-induced height variations without violating manufacturing design rules.
4Productivity
If metal fill pattern is created with maximum density, then CMP efficiency improves, but design rule violations occur
Solution Approach 1:
The patent changes the metal fill pattern parameters by systematically varying metal segment widths, spacings, and arrangements to achieve maximum density while staying within design rule constraints. The system iteratively optimizes these parameters to push the boundaries of what is permissible under design rules, maximizing metal presence for CMP efficiency without causing violations.
Solution Approach 2:
The patent employs dynamic adjustment of metal fill patterns by providing different fill densities and patterns for different TDV regions based on their specific geometries and surrounding structures. The system dynamically selects appropriate fill strategies (e.g., different segment arrangements, varying densities) to maximize metal presence while adapting to local design rule requirements in each region.
Data Source
AI summary
Method, apparatus, and computer readable medium for designing an integrated circuit (IC) are described. In some examples, layout data describing conductive layers of the integrated circuit is obtained. The layout data is analyzed to identify through die via (TDV) areas. A metal fill pattern is created for each of the TDV areas having a maximum metal density within design rules for the integrated circuit. The metal fill pattern for each of the TDV areas is merged with the layout data.