Metal-Containing Fin Isolation for Precise Nanowire Gate Cuts
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving precise control over feature dimensions and spacing as transistors scale down, particularly in multi-gate and nanowire transistors, where conventional lithographic processes face limitations in maintaining mobility and short channel control, leading to complexities in fin trim isolation processes.
Innovation Solution
The implementation of metal-containing fin isolation regions, where a dielectric material with a metal oxide upper portion is used in the fin trim isolation process, either post-replacement gate or pre-replacement gate, to facilitate fewer processing operations and reduce interference with metal gate processing, enabling selective etching and self-assembly techniques for improved precision and selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional lithographic processes are used to pattern features in multi-gate and nanowire transistors, then feature dimensions can be reduced for increased device density, but control over mobility and short channel effects deteriorates
Solution Approach 1:
The patent segments the isolation structure into multiple portions: a first isolation portion with a first dielectric material and a second isolation portion with a second dielectric material having different etch selectivity. This segmentation allows different regions to serve different functions - one region provides electrical isolation while the other enables selective processing, thereby maintaining device performance while enabling continued scaling.
Solution Approach 2:
The patent introduces a mandrel structure as an intermediary element in the fin trim isolation process. The mandrel serves as a temporary placeholder that defines the fin width during processing, and is later removed to create the final fin structure. This intermediary approach enables precise control over fin dimensions and isolation characteristics without directly constraining the final device performance parameters.
2Manufacturing precision
If fin trim isolation processes are made more complex to achieve precise dimension control, then manufacturing precision improves, but processing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the mandrel structure and first isolation portion before final fin patterning. These preliminary structures pre-define the geometric constraints and isolation characteristics needed for precise fin trim, eliminating the need for complex post-processing adjustments and reducing overall process complexity.
Solution Approach 2:
The patent utilizes parameter changes in the form of selective etching based on dielectric material properties. By changing the etch selectivity parameter between different dielectric materials, the process achieves high precision fin trim isolation through a single etching step rather than multiple sequential steps, thereby improving manufacturing precision while reducing processing complexity.
3Productivity
If metal gate processing is performed with conventional isolation structures, then device fabrication can proceed, but interference with work function metal deposition occurs
Solution Approach 1:
The patent applies local quality by providing different dielectric materials in different spatial regions - the first dielectric material in the first isolation portion and the second dielectric material in the second isolation portion. This local differentiation ensures that the isolation structure adjacent to the metal gate has properties optimized for metal gate processing, preventing interference with work function metal deposition while maintaining electrical isolation elsewhere.
Solution Approach 2:
The mandrel structure serves as a disposable temporary element that facilitates the fabrication process but is ultimately removed. This disposable approach enables complex fin trim isolation to be achieved through simple, sequential processing steps without requiring permanent complex structures that would interfere with subsequent metal gate processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision of fin trim isolation, reduces processing complexity, and ensures seamless work function metal deposition, thereby improving the overall performance and reliability of integrated circuit structures by alleviating space constraints and enabling tighter pitch scaling.
Implementation Method 1
at least the upper portion of the dielectric material includes a metal... to facilitate fewer processing operations and reduce interference with metal gate processing, enabling selective etching
Implementation Method 2
enabling selective etching and self-assembly techniques for improved precision and selectivity
Data Source
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Figure 1C
AI summary
Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate plug includes a metal-containing dielectric material.