Metal Floating Gate Non-Volatile Memory Cell Height Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Scaling down the height of non-volatile memory cells to match logic devices on the same wafer is challenging due to issues with polysilicon gate thickness leading to ballistic transport of electrons, causing reliability problems during program and erase operations.
Innovation Solution
The use of metal floating and control gates over a silicon substrate, with high-K dielectric insulation layers and polysilicon erase and word line gates, reduces the overall height of the memory cells and minimizes ballistic transport by employing metal layers like TaN, TiN, and TiAl, and high-K dielectric materials to improve coupling ratios and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If polysilicon floating gate thickness is scaled down to reduce memory cell height, then memory cell height is reduced, but ballistic transport of electrons occurs causing reliability issues
Solution Approach 1:
The patent changes the material parameter from polysilicon to metal (such as tungsten, titanium nitride, or tantalum nitride) for the floating gate, which fundamentally alters the electrical transport properties. This material substitution enables thinner gate structures (reducing height from 120nm to 60-70nm) while preventing ballistic electron transport that plagues polysilicon gates at scaled dimensions.
Solution Approach 2:
The patent employs composite material structures including metal floating gates combined with high-k dielectric materials (such as hafnium oxide or silicon oxynitride) in the tunnel barrier and inter-poly dielectric layers. This composite approach enables effective coupling and charge storage while maintaining reduced cell height and preventing harmful electron transport phenomena.
2Length of stationary object
If polysilicon control gate thickness is scaled down to reduce memory cell height, then memory cell height is reduced, but coupling ratio deteriorates
Solution Approach 1:
The patent changes the control gate material from polysilicon to metal, which has superior electrical conductivity and charge storage capabilities. This material parameter change enables thinner gate structures while maintaining or even improving the coupling ratio between the control gate and floating gate, as metal gates provide more efficient electric field coupling.
Solution Approach 2:
The patent utilizes high-k dielectric materials in combination with metal gates to achieve enhanced coupling ratios. The high-k material (such as hafnium oxide or silicon oxynitride) in the tunnel barrier and inter-poly dielectric layers works synergistically with the metal gate to provide strong electric field coupling while enabling reduced gate thickness and overall cell height.
3Adaptability or versatility
If memory cell height is reduced to match logic devices, then compatibility with logic devices improves, but polysilicon gate reliability deteriorates due to ballistic transport
Solution Approach 1:
The patent fundamentally changes the gate material parameter from polysilicon to metal, which resolves the reliability issue while enabling height reduction. Metal gates do not exhibit ballistic transport at the scaled dimensions required for logic device compatibility, thus simultaneously achieving both compatibility and reliability.
Solution Approach 2:
The patent employs composite structures of metal gates with high-k dielectric materials to achieve the required height reduction for logic device compatibility while maintaining reliability. The combination of metal (providing excellent electrical properties) and high-k dielectric (providing strong coupling and charge retention) creates a robust structure that is both compatible with scaled logic devices and reliable in operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the height of non-volatile memory cells from 120 nm to 60-70 nm, enhancing reliability and program performance while suppressing tunneling leakage and ballistic current issues.
Implementation Method 1
scaling down the thickness of the polysilicon floating gate can result in ballistic transport of electrons through the floating gate and into the inter-poly dielectric during program and/or erase operations
Implementation Method 2
suppressing tunneling leakage and ballistic current issues
Implementation Method 3
high-K dielectric insulation layers and polysilicon erase and word line gates
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.