Selective Metal Fuse Thickness Reduction via Wet Etching
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Solution Overview
Problem
In integrated circuit (IC) fabrication, there is a tradeoff between achieving low resistance interconnect lines and easily removable fuse lines, as both often share the same metal layer, leading to higher laser pulse energy requirements for trimming, which can cause damage and inefficiencies such as fluctuation in trimming efficiency, metal residue, and inter-layer dielectric cracking.
Innovation Solution
The process involves depositing a first dielectric layer over a semiconductor structure, patterning a first metal layer to form metal lines, and then selectively reducing the thickness of specific metal lines to create thinner fuse lines using wet etching, without altering the thickness of unselected lines, thereby facilitating easier laser trimming while maintaining conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal fuse lines are made thicker to reduce resistance, then interconnect line performance improves, but laser trimming becomes more difficult and requires higher energy
Solution Approach 1:
The patent applies local quality by creating different thicknesses of metal lines in different locations. Specifically, fuse lines are made thinner (e.g., 0.5 μm) while interconnect lines maintain their original thickness (e.g., 1.0 μm). This is achieved through selective etching processes that remove metal only from fuse line regions, allowing each type of line to have optimized properties for its specific function.
2Ease of repair
If higher laser pulse energy is used to trim thicker metal fuse lines, then fuse lines can be removed, but damage to lower layers, substrate, and neighboring structures increases
Solution Approach 1:
The patent changes the physical parameter of metal line thickness specifically for fuse lines. By reducing fuse line thickness from the standard interconnect thickness (e.g., 1.0 μm) to a thinner dimension (e.g., 0.5 μm), the laser trimming process requires lower pulse energy. This parameter change enables effective fuse trimming while avoiding damage to underlying layers and the substrate.
3Productivity
If higher laser energy is used for trimming thicker fuse lines, then trimming can proceed, but trimming efficiency fluctuates and metal residue increases
Solution Approach 1:
The patent implements local quality by differentiating fuse line thickness from interconnect line thickness. Fuse lines are selectively made thinner through targeted etching processes, ensuring they have uniform reduced thickness optimized for clean laser trimming. This local differentiation eliminates trimming efficiency fluctuations and prevents metal residue issues that would occur with thicker, non-uniform fuse lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient laser trimming of fuse lines with reduced metal residue and inter-layer dielectric cracking, improving the overall process efficiency and minimizing damage to adjacent structures.
Implementation Method 1
One technique by which the first metal lines can be reduced is wet etching in a timed etch that removes a known amount of metal to reduce the thickness of the metal lines where the fuse is present.
Data Source
AI summary
Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.