Metal Gate Separation Air Gap for Lower FinFET Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor manufacturing processes for FinFET devices face challenges with increased extrinsic capacitance due to the use of silicon nitride in gate end cuts and the constrained dummy poly/oxide removal process, which affects the interfacial layer and high-k dielectric refill window.
Innovation Solution
The introduction of a gate separation structure using one or more layers of dielectric material and an air gap to reduce extrinsic capacitance, achieved through a manufacturing process involving the formation of a sacrificial layer, liner layers, and the creation of an air gap between metal gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If silicon nitride is used in gate end cuts, then gate structure integrity is improved, but extrinsic capacitance increases
Solution Approach 1:
The patent changes the dielectric material parameter from silicon nitride (high-k) to air gap (k≈1), fundamentally altering the electrical properties of the gate end cut region. This parameter change directly reduces extrinsic capacitance while maintaining structural integrity through the air gap configuration between adjacent gate electrodes.
2Productivity
If dummy gate removal is performed early, then manufacturing process efficiency is improved, but interfacial layer and high-k dielectric refill window are constrained
Solution Approach 1:
The patent performs dummy gate removal as a preliminary action before forming the air gap structure. This preliminary removal creates the necessary space for subsequent air gap formation while maintaining process efficiency. The sequence is optimized to enable both high productivity and adequate refill window for interfacial layer and high-k dielectric formation.
3Object-generated harmful factors
If air gap is formed by removing sacrificial layer, then extrinsic capacitance is reduced, but process complexity increases
Solution Approach 1:
The patent uses a sacrificial layer as an intermediary material that is temporarily deposited, patterned, and then removed to create the air gap structure. This intermediary approach simplifies the overall process by using a standard deposition-etch-remove sequence rather than attempting to directly form air gaps, thereby reducing process complexity while achieving the desired capacitance reduction.
Solution Approach 2:
The patent employs oxygen plasma as a strong oxidant to remove the carbon-based sacrificial layer through oxidation. This accelerated oxidation process efficiently converts the sacrificial material into volatile products that can be evacuated, creating clean air gaps without requiring complex mechanical or chemical removal processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces extrinsic capacitance and improves the manufacturing process by allowing for better control over the gate dielectric refill window and reducing parasitic capacitance between adjacent gate electrodes.
Implementation Method 1
removing the recessed sacrificial layer using UV radiation or oxygen plasma
Implementation Method 2
removing the recessed sacrificial layer using UV radiation or oxygen plasma
Implementation Method 3
removing the recessed sacrificial layer using UV radiation or oxygen plasma
Data Source
AI summary
In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.