Metal Gate Air-Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor devices for augmented reality (AR) and virtual reality (VR) applications face challenges due to the use of long wires and metal interconnections, which consume space and complicate mounting, especially in head-mounted displays.
Innovation Solution
A semiconductor device is fabricated with a metal gate on a substrate, featuring a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, with air gaps formed between the layers to reduce capacitance and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If long wires and metal interconnections are used to connect DDICs to display modules, then the device can be mounted and connected, but the space consumption increases and mounting difficulty increases
Solution Approach 1:
The patent introduces air gaps in the vertical dimension between the DDIC substrate and display module, allowing connections to be made in three-dimensional space rather than requiring long horizontal wire runs. This dimensional transition reduces the planar area occupied by interconnections while maintaining electrical connectivity.
Solution Approach 2:
The patent embeds air gaps within the layered structure of the display device, nesting the void spaces between functional layers (DDIC, color filter, liquid crystal layer, etc.). This nested arrangement allows the system to maintain compact form factor while providing necessary electrical isolation and mechanical flexibility.
2Device complexity
If traditional metal gate structure is used, then the device structure is simple, but the gate-source and gate-drain capacitance are high which limits slew rate
Solution Approach 1:
The patent applies different dielectric properties to different regions of the gate structure by introducing air gaps specifically in the gate-source and gate-drain overlap regions. This local modification reduces parasitic capacitance where it most impacts performance while maintaining the overall simplicity of the metal gate structure.
Solution Approach 2:
The patent changes the dielectric parameter (permittivity) in specific regions by replacing solid dielectric material with air gaps. This parameter change directly reduces the capacitance value in the gate overlap regions, thereby increasing the slew rate without fundamentally altering the metal gate architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gaps lower gate-source and gate-drain capacitance, enhancing the slew rate of display driver integrated circuits (DDICs) and reducing device size.
Implementation Method 1
The air gaps lower gate-source and gate-drain capacitance, enhancing the slew rate of display driver integrated circuits (DDICs)
Data Source
AI summary
A semiconductor device includes a metal gate on a substrate, a spacer adjacent to the metal gate, an interlayer dielectric (ILD) layer around the metal gate, a first air gap adjacent to one side of the metal gate and between the spacer and the metal gate, and a second air gap adjacent to another side of the metal gate and between the spacer and the metal gate. Preferably, the metal gate includes a high-k dielectric layer on the substrate, a work function metal (WFM) layer on the high-k dielectric layer, and a low resistance metal layer on the WFM layer.