Metal Gate Structure Amorphous Region Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable devices with increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and leading to issues with doped impurities channeling through the crystal lattice and resulting in reduced Ion/Ioff ratio and high contact resistance.
Innovation Solution
The implementation of a two-stage pre-amorphized implantation (PAI) process, where the first PAI forms amorphous regions before the dielectric spacer liner (DSL) layer and the second PAI increases their thickness, followed by self-aligned silicidation, to ensure sufficient size of amorphous and metal silicide regions, preventing excessive dopant channeling and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process reliability deteriorates and dopant channeling increases
Solution Approach 1:
The patent divides the single PAI process into two separate implantation steps: first PAI before DSL layer formation, and second PAI after DSL layer formation. This segmentation allows each implantation to be optimized independently for different depth requirements, preventing dopant channeling while maintaining scalability for high-volume manufacturing
Solution Approach 2:
The first PAI is performed as a preliminary action before the DSL layer is formed, creating initial amorphous regions that prevent dopant channeling. This preliminary amorphization establishes a foundation that controls subsequent dopant behavior during the second implantation and silicidation processes
2Reliability
If amorphous region thickness is increased to prevent dopant channeling, then Ion/Ioff ratio is improved, but additional processing steps are required
Solution Approach 1:
The patent combines the formation of amorphous regions with the DSL layer structure itself. The DSL layer serves dual purposes: as a spacer defining contact alignment and as a template for controlled amorphous region thickness. This merging eliminates the need for separate amorphous layer formation steps while achieving the required thickness control
Solution Approach 2:
The patent changes the implantation parameters between the two PAI steps: first PAI uses lower dose and energy to create initial amorphous regions, while second PAI uses higher dose and energy to increase amorphous region thickness. This parameter optimization achieves reliable dopant channeling prevention without excessive processing complexity
3Reliability
If metal silicide region size is increased to reduce contact resistance, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned silicidation where the metal silicide forms automatically in the amorphous regions created by PAI. The amorphous regions themselves define the silicide formation boundaries, eliminating the need for separate patterning steps and reducing manufacturing precision requirements while ensuring uniform silicide region size for low contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the Ion/Ioff ratio and reduces contact resistance by forming larger amorphous and metal silicide regions, thereby improving device performance and reliability.
Implementation Method 1
performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region
Implementation Method 2
forming amorphous regions before the dielectric spacer liner (DSL) layer and the second PAI increases their thickness
Data Source
AI summary
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.